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User Pratyush Priyam Kuan
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Answers by Pratyush Priyam Kuan
8
votes
1
GATE CSE 2008 | Question: 33, ISRO2009-80
Which of the following is/are true of the auto-increment addressing mode? It is useful in creating self-relocating code If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation The amount of increment depends on the size of the data item accessed I only II only III only II and III only
answered
in
CO and Architecture
Nov 7, 2020
14.3k
views
gatecse-2008
addressing-modes
co-and-architecture
normal
isro2009
3
votes
2
GATE CSE 1993 | Question: 6.2
If the state machine described in figure should have a stable state, the restriction on the inputs is given by $a.b=1$ $a+b=1$ $\bar{a} + \bar{b} =0$ $\overline{a.b}=1$ $\overline{a+b} =1$
answered
in
Digital Logic
Oct 4, 2020
5.7k
views
gate1993
digital-logic
normal
circuit-output
sequential-circuit
0
votes
3
GATE CSE 2006 | Question: 40
Consider numbers represented in 4-bit Gray code. Let $ h_{3}h_{2}h_{1}h_{0}$ be the Gray code representation of a number $n$ and let $ g_{3}g_{2}g_{1}g_{0}$ be the Gray code of $ (n+1)(modulo 16)$ ... $ g_{3}(h_{3}h_{2}h_{1}h_{0})=\sum (0,1,6,7,10,11,12,13) $
answered
in
Digital Logic
Sep 29, 2020
15.4k
views
gatecse-2006
digital-logic
number-representation
binary-codes
normal
1
vote
4
GATE CSE 1999 | Question: 1.21
The maximum gate delay for any output to appear in an array multiplier for multiplying two $n$ bit numbers is $O(n^2)$ $O(n)$ $O(\log n)$ $O(1)$
answered
in
Digital Logic
Sep 29, 2020
9.6k
views
gate1999
digital-logic
normal
array-multiplier
0
votes
5
NIELIT 2016 DEC Scientist B (IT) - Section B: 11
What is the meaning of following declaration? int(*p[7])(); $p$ is pointer to function $p$ is pointer to such function which return type is array $p$ is array of pointer to function $p$ is pointer to array of function
answered
in
Programming
Jun 6, 2020
736
views
nielit2016dec-scientistb-it
programming-in-c
pointers
array-of-pointers
2
votes
6
Instruction Execution
Consider the 2 GHz clock frequency processor used execute the following program segment. Assume the 3 clock cycles required for Register to/from memory transfer, 1 clock cycle for ADD with both operands in register, 2 clock cycle MUL with both operands in ... for instruction fetch and decode. What is the total time required to complete the program execution (in ns)? Ans. 18
answered
in
CO and Architecture
Mar 15, 2020
1.5k
views
co-and-architecture
machine-instructions
0
votes
7
please explain
answered
in
CO and Architecture
Mar 12, 2020
396
views
dma
0
votes
8
Overflow condition
The overflow condition for unsigned 8 bit integer would be if c= a+b if c<a Or c< b The overflow condition for signed 8 bit integer would be if c= a+b if c<a and c< b right ??
answered
in
CO and Architecture
Mar 11, 2020
716
views
co-and-architecture
0
votes
9
No. of 1-address instructions
A computer system supports 1-address instructions and 2-address instructions and word size is 16 bits. Main memory is 64 words. If there are eight 2 -address instructions then how many 1-address instructions are used?
answered
in
CO and Architecture
Mar 10, 2020
4.2k
views
0
votes
10
Calculate effective address?
answered
in
CO and Architecture
Mar 10, 2020
3.8k
views
co-and-architecture
5
votes
11
GATE CSE 1996 | Question: 2.25
A micro program control unit is required to generate a total of $25$ control signals. Assume that during any micro instruction, at most two control signals are active. Minimum number of bits required in the control word to generate the required control signals will be: $2$ $2.5$ $10$ $12$
answered
in
CO and Architecture
Mar 10, 2020
20.4k
views
gate1996
co-and-architecture
microprogramming
normal
0
votes
12
An instruction takes m bits .It suppourts 0 address(p), 1 address(q),2 address(r) , a memory reference requires n bits . Establish a relation between p,q,r,n,m
answered
in
CO and Architecture
Mar 10, 2020
379
views
0
votes
13
GATE CSE 2014 Set 1 | Question: 55
Consider two processors $P_1$ and $P_2$ executing the same instruction set. Assume that under identical conditions, for the same input, a program running on $P_2$ takes $\text{25%}$ less time but incurs $\text{20%}$ more CPI (clock cycles per instruction) ... If the clock frequency of $P_1$ is $\text{1GHZ}$, then the clock frequency of $P_2$ (in GHz) is ______.
answered
in
CO and Architecture
Mar 9, 2020
14.7k
views
gatecse-2014-set1
co-and-architecture
numerical-answers
normal
speedup
1
vote
14
GATE CSE 2014 Set 2 | Question: 44
If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected? Width of tag comparator Width of set index decoder Width of way selection multiplexer Width of processor to main memory data bus
answered
in
CO and Architecture
Mar 9, 2020
7.9k
views
gatecse-2014-set2
co-and-architecture
cache-memory
normal
1
vote
15
GATE CSE 1998 | Question: 18
For a set-associative Cache organization, the parameters are as follows: ... $1 \leq m \leq l$. Give the value of the hit ratio for $l = 1$.
answered
in
CO and Architecture
Mar 8, 2020
6.1k
views
gate1998
co-and-architecture
cache-memory
descriptive
0
votes
16
GATE CSE 2006 | Question: 09, ISRO2009-35
A CPU has $24$-$bit$ instructions. A program starts at address $300$ (in decimal). Which one of the following is a legal program counter (all values in decimal)? $400$ $500$ $600$ $700$
answered
in
CO and Architecture
Mar 7, 2020
13.0k
views
gatecse-2006
co-and-architecture
machine-instructions
easy
isro2009
2
votes
17
GATE CSE 2007 | Question: 37, ISRO2009-37
Consider a pipelined processor with the following four stages: IF: Instruction Fetch ID: Instruction Decode and Operand Fetch EX: Execute WB: Write Back The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX ... $ R5$-$R4} \\ \end{array}$ $7$ $8$ $10$ $14$
answered
in
CO and Architecture
Mar 7, 2020
11.7k
views
gatecse-2007
co-and-architecture
pipelining
normal
isro2009
1
vote
18
GATE CSE 2007 | Question: 54
In a simplified computer the instructions are: ... computation should be in memory. What is the minimum number of MOV instructions in the code generated for this basic block? $2$ $3$ $5$ $6$
answered
in
CO and Architecture
Mar 7, 2020
10.3k
views
gatecse-2007
co-and-architecture
machine-instructions
normal
1
vote
19
GATE CSE 2008 | Question: 34
Which of the following must be true for the RFE (Return From Exception) instruction on a general purpose processor? It must be a trap instruction It must be a privileged instruction An exception cannot be allowed to occur during execution of an RFE instruction I only II only I and II only I, II and III only
answered
in
CO and Architecture
Mar 7, 2020
9.6k
views
gatecse-2008
co-and-architecture
machine-instructions
normal
0
votes
20
GATE CSE 1991 | Question: 01,ii
In interleaved memory organization, consecutive words are stored in consecutive memory modules in _______ interleaving, whereas consecutive words are stored within the module in ________ interleaving.
answered
in
CO and Architecture
Mar 5, 2020
1.9k
views
gate1991
co-and-architecture
normal
memory-interfacing
out-of-gate-syllabus
2
votes
21
GATE CSE 2008 | Question: 71
Consider a machine with a $2$-way set associative data cache of size $64\text{Kbytes}$ and block size $16\text{bytes}$. The cache is managed using $32\;\text{bit}$ virtual addresses and the page size is $4\text{Kbytes}$. A program to be run on this ... total size of the tags in the cache directory is: $32\text{Kbits}$ $34\text{Kbits}$ $64\text{Kbits}$ $68\text{Kbits}$
answered
in
CO and Architecture
Mar 5, 2020
14.2k
views
gatecse-2008
co-and-architecture
cache-memory
normal
1
vote
22
GATE CSE 2000 | Question: 1.8
Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non-pipelined but identical CPU, we can say that T1 ≤ T2 T1 ≥ T2 T1 < T2 T1 and T2 plus the time taken for one instruction fetch cycle
answered
in
CO and Architecture
Mar 4, 2020
9.2k
views
gatecse-2000
pipelining
co-and-architecture
easy
0
votes
23
GATE CSE 2005 | Question: 7
The time complexity of computing the transitive closure of a binary relation on a set of $n$ elements is known to be: $O(n)$ $O(n \log n)$ $O \left( n^{\frac{3}{2}} \right)$ $O\left(n^3\right)$
answered
in
Set Theory & Algebra
Mar 2, 2020
21.4k
views
gatecse-2005
set-theory&algebra
normal
relations
2
votes
24
GATE CSE 2002 | Question: 3
Let $A$ be a set of $n(>0)$ elements. Let $N_r$ be the number of binary relations on $A$ and let $N_f$ be the number of functions from $A$ to $A$ Give the expression for $N_r,$ in terms of $n.$ Give the expression for $N_f,$ terms of $n.$ Which is larger for all possible $n,N_r$ or $N_f$
answered
in
Set Theory & Algebra
Mar 2, 2020
3.0k
views
gatecse-2002
set-theory&algebra
normal
descriptive
relations
1
vote
25
GATE CSE 2000 | Question: 2.5
A relation $R$ is defined on the set of integers as $xRy$ iff $(x + y)$ is even. Which of the following statements is true? $R$ is not an equivalence relation $R$ is an equivalence relation having $1$ equivalence class $R$ is an equivalence relation having $2$ equivalence classes $R$ is an equivalence relation having $3$ equivalence classes
answered
in
Set Theory & Algebra
Mar 2, 2020
11.2k
views
gatecse-2000
set-theory&algebra
relations
normal
0
votes
26
GATE CSE 1999 | Question: 3
Mr. X claims the following: If a relation R is both symmetric and transitive, then R is reflexive. For this, Mr. X offers the following proof: “From xRy, using symmetry we get yRx. Now because R is transitive xRy and yRx together imply xRx. Therefore, R is reflexive”. Give an example of a relation R which is symmetric and transitive but not reflexive.
answered
in
Set Theory & Algebra
Mar 2, 2020
2.2k
views
gate1999
set-theory&algebra
relations
normal
descriptive
0
votes
27
GATE CSE 1998 | Question: 1.6
Suppose $A$ is a finite set with $n$ elements. The number of elements in the largest equivalence relation of A is $n$ $n^2$ $1$ $n+1$
answered
in
Set Theory & Algebra
Mar 2, 2020
7.7k
views
gate1998
set-theory&algebra
relations
easy
0
votes
28
GATE CSE 2017 Set 2 | Question: 21
Consider the set $X=\{a, b, c, d, e\}$ under partial ordering $R=\{(a,a), (a, b), (a, c), (a, d), (a, e), (b, b), (b, c), (b, e), (c, c), (c, e), (d, d), (d, e), (e, e) \}$ The Hasse diagram of the partial order $(X, R)$ is shown below. The minimum number of ordered pairs that need to be added to $R$ to make $(X, R)$ a lattice is ______
answered
in
Set Theory & Algebra
Mar 1, 2020
8.9k
views
gatecse-2017-set2
set-theory&algebra
lattice
numerical-answers
normal
2
votes
29
GATE CSE 1988 | Question: 2xviii
Show that if $G$ is a group such that $(a. b)^2 = a^2.b^2$ for all $a, b$ belonging to $G$, then $G$ is an abelian.
answered
in
Set Theory & Algebra
Feb 29, 2020
1.1k
views
gate1988
descriptive
group-theory
0
votes
30
TIFR CSE 2013 | Part B | Question: 16
Consider a function $T_{k, n}: \left\{0, 1\right\}^{n}\rightarrow \left\{0, 1\right\}$ which returns $1$ if at least $k$ of its $n$ inputs are $1$. Formally, $T_{k, n}(x)=1$ if $\sum ^{n}_{1} x_{i}\geq k$. Let $y \in \left\{0, 1\right\}^{n}$ ... $y_{i}$ is omitted) is equivalent to $T_{k-1}, n(y)$ $T_{k, n}(y)$ $y_{i}$ $\neg y_{i}$ None of the above
answered
in
Set Theory & Algebra
Feb 29, 2020
985
views
tifr2013
set-theory&algebra
functions
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