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0
votes
1
ISI2019MMA15
The rank of the matrix $\begin{bmatrix} 0 &1 &t \\ 2& t & 1\\ 2& 2 & 0 \end{bmatrix}$ equals $3$ for any real number $t$ $2$ for any real number $t$ $2$ or $3$ depending on the value of $t$ $1,2$ or $3$ depending on the value of $t$
answered
May 7, 2019
in
Linear Algebra

169
views
isi2019mma
linearalgebra
engineeringmathematics
matrices
0
votes
2
GATE201020
Which of the following concurrency control protocols ensure both conflict serializability and freedom from deadlock? 2phase locking Timestamp ordering I only II only Both I and II Neither I nor II
answered
Feb 23, 2019
in
Databases

7.7k
views
gate2010
databases
transactions
normal
–1
vote
3
GATE201935
Consider the first order predicate formula $\varphi$: $\forall x [ ( \forall z \: z \mid x \Rightarrow (( z=x) \vee (z=1))) \rightarrow \exists w ( w > x) \wedge (\forall z \: z \mid w \Rightarrow ((w=z) \vee (z=1)))]$ Here $a \mid b$ ... Set of all positive integers $S3:$ Set of all integers Which of the above sets satisfy $\varphi$? S1 and S2 S1 and S3 S2 and S3 S1, S2 and S3
answered
Feb 8, 2019
in
Mathematical Logic

5.8k
views
gate2019
engineeringmathematics
discretemathematics
mathematicallogic
firstorderlogic
+1
vote
4
TIFR2010B38
Suppose three coins are lying on a table, two of them with heads facing up and one with tails facing up. One coin is chosen at random and flipped. What is the probability that after the flip the majority of the coins(i.e., at least two of them) will have heads facing up? ... $\left(\frac{1}{4}\right)$ $\left(\frac{1}{4}+\frac{1}{8}\right)$ $\left(\frac{2}{3}\right)$
answered
Dec 25, 2018
in
Probability

1k
views
tifr2010
probability
binomialdistribution
0
votes
5
GATE201432
Let $X$ and $Y$ be finite sets and $f:X \to Y$ be a function. Which one of the following statements is TRUE? For any subsets $A$ and $B$ of $X, fA \cup B = f(A) + f(B)$ For any subsets $A$ and $B$ of $X, f(A \cap B) = f(A) \cap f(B)$ For any subsets $A$ and $B$ ... $S$ and $T$ of $Y, f^{1}(S \cap T) = f^{1}(S) \cap f^{1}(T)$
answered
Dec 17, 2018
in
Set Theory & Algebra

4.4k
views
gate20143
settheory&algebra
functions
normal
0
votes
6
GATE198710e
Show that the conclusion $(r \to q)$ follows from the premises: $p, (p \to q) \vee (p \wedge (r \to q))$
answered
Dec 5, 2018
in
Mathematical Logic

800
views
gate1987
mathematicallogic
propositionallogic
proof
descriptive
0
votes
7
GATE200579
Consider the following data path of a CPU. The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation ... = R0 + R1. The minimum number of clock cycles needed for execution cycle of this instruction is: $2$ $3$ $4$ $5$
answered
Nov 13, 2018
in
CO and Architecture

7.5k
views
gate2005
coandarchitecture
machineinstructions
datapath
normal
+1
vote
8
GATE200772
Consider the following program segment. Here $\text{R1, R2}$ and $\text{R3}$ ... memory is word addressable. After the execution of this program, the content of memory location $2010$ is: $100$ $101$ $102$ $110$
answered
Nov 10, 2018
in
CO and Architecture

2.7k
views
gate2007
coandarchitecture
machineinstructions
interrupts
normal
0
votes
9
GATE200771
Consider the following program segment. Here $\text{R1, R2}$ and $\text{R3}$ ... is word addressable. The number of memory references for accessing the data in executing the program completely is $10$ $11$ $20$ $21$
answered
Nov 10, 2018
in
CO and Architecture

6.5k
views
gate2007
coandarchitecture
machineinstructions
interrupts
normal
0
votes
10
GATE2007IT6, ISRO201125
A processor takes $12$ cycles to complete an instruction I. The corresponding pipelined processor uses $6$ stages with the execution times of $3, 2, 5, 4, 6$ and $2$ cycles respectively. What is the asymptotic speedup assuming that a very large number of instructions are to be executed? $1.83$ $2$ $3$ $6$
answered
Nov 10, 2018
in
CO and Architecture

4.7k
views
gate2007it
coandarchitecture
pipelining
normal
isro2011
0
votes
11
GATE2006IT79
A pipelined processor uses a 4stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The arithmetic operations as well as the load and store operations are carried out in the EX stage. ... stage is used. The number of clock cycles required to complete the sequence of instructions is $10$ $12$ $14$ $16$
answered
Nov 10, 2018
in
CO and Architecture

5.5k
views
gate2006it
coandarchitecture
pipelining
normal
+1
vote
12
GATE2015249
Consider a typical disk that rotates at $15000$ rotations per minute (RPM) and has a transfer rate of $50 \times 10^6$ bytes/sec. If the average seek time of the disk is twice the average rotational delay and the controller's transfer time is $10$ times the disk transfer time, the average time (in milliseconds) to read or write a $512$byte sector of the disk is _____
answered
Nov 9, 2018
in
Operating System

5.3k
views
gate20152
operatingsystem
disks
normal
numericalanswers
+2
votes
13
GATE2015148
Consider a disk pack with a seek time of $4$ milliseconds and rotational speed of $10000$ rotations per minute (RPM). It has $600$ sectors per track and each sector can store $512$ bytes of data. Consider a file stored in the disk. The ... each sector is half of the time for one complete rotation. The total time (in milliseconds) needed to read the entire file is__________________
answered
Nov 9, 2018
in
Operating System

6.9k
views
gate20151
operatingsystem
disks
normal
numericalanswers
+1
vote
14
GATE201329
Consider a hard disk with $16$ recording surfaces $(015)$ having 16384 cylinders $(016383)$ and each cylinder contains $64$ sectors $(063)$. Data storage capacity in each sector is $512$ bytes. Data are organized cylinderwise and the addressing format is < ... the cylinder number of the last sector of the file, if it is stored in a contiguous manner? $1281$ $1282$ $1283$ $1284$
answered
Nov 9, 2018
in
Operating System

8.8k
views
gate2013
operatingsystem
disks
normal
0
votes
15
GATE2016131
The size of the data count register of a $\text{DMA}$ controller is $16 \text{bits}$. The processor needs to transfer a file of $29,154$ kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the $\text{DMA}$ controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is _________.
answered
Nov 5, 2018
in
CO and Architecture

5.5k
views
gate20161
coandarchitecture
dma
normal
numericalanswers
0
votes
16
GATE200468
A hard disk with a transfer rate of $10$ Mbytes/second is constantly transferring data to memory using DMA. The processor runs at $600$ MHz, and takes $300$ and $900$ clock cycles to initiate and complete DMA transfer respectively. If the size of the transfer is $20$ Kbytes, what is the percentage of processor time consumed for the transfer operation? $5.0 \%$ $1.0\%$ $0.5\%$ $0.1\%$
answered
Nov 5, 2018
in
CO and Architecture

8.7k
views
gate2004
dma
normal
coandarchitecture
+2
votes
17
GATE200580
The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation  the first one for loading address in ... $2$ $3$ $4$ $5$
answered
Nov 3, 2018
in
CO and Architecture

6.7k
views
coandarchitecture
normal
gate2005
datapath
machineinstructions
0
votes
18
GATE200858
A computer on a $10$ $Mbps$ network is regulated by a token bucket. The token bucket is filled at a rate of $2$ $Mbps$. It is initially filled to capacity with $16$ $Megabits$. What is the maximum duration for which the computer can transmit at the full $10$ $Mbps$? $1.6$ seconds $2$ seconds $5$ seconds $8$ seconds
answered
Sep 10, 2018
in
Computer Networks

5.5k
views
gate2008
computernetworks
tokenbucket
0
votes
19
GATE2005IT85b
Consider a simple graph with unit edge costs. Each node in the graph represents a router. Each node maintains a routing table indicating the next hop router to be used to relay a packet to its destination and the cost of the path to the destination through that router. Initially, the routing ... $(t + 100)$ is : $>100$ but finite $\infty$ $3$ $>3$ and $\leq 100$
answered
Sep 10, 2018
in
Computer Networks

5.1k
views
gate2005it
computernetworks
routing
normal
+1
vote
20
GATE200418, ISRO200731
In an $SR$ latch made by crosscoupling two NAND gates, if both $S$ and $R$ inputs are set to $0$, then it will result in $Q = 0, Q' = 1$ $Q = 1, Q' = 0$ $Q = 1, Q' = 1$ Indeterminate states
answered
Aug 18, 2018
in
Digital Logic

6.7k
views
gate2004
digitallogic
easy
isro2007
flipflop
+2
votes
21
GATE2015137
A positive edgetriggered $D$ flipflop is connected to a positive edgetriggered $JK$ flipflop as follows. The $Q$ output of the $D$ flipflop is connected to both the $J$ and $K$ inputs of the $JK$ flipflop, while the $Q$ output of ... of the $JK$ flipflops. Both the flipflops have nonzero propagation delays. $0110110\ldots$ $0100100\ldots$ $011101110\ldots$ $011001100\ldots$
answered
Aug 17, 2018
in
Digital Logic

4.6k
views
gate20151
digitallogic
flipflop
normal
+1
vote
22
GATE2014242
Consider the C function given below. int f(int j) { static int i = 50; int k; if (i == j) { printf("something"); k = f(i); return 0; } else return 0; } Which one of the following is TRUE? The function returns $0$ for all values of $j$. The ... $j$. The function returns $0$ when $j = 50$. The function will exhaust the runtime stack or run into an infinite loop when $j = 50$.
answered
Jul 31, 2018
in
Programming

2k
views
gate20142
programming
programminginc
0
votes
23
GATE2014142
Consider the following pseudo code. What is the total number of multiplications to be performed? D = 2 for i = 1 to n do for j = i to n do for k = j + 1 to n do D = D * 3 Half of the product of the $3$ consecutive integers. Onethird of the product of the $3$ consecutive integers. Onesixth of the product of the $3$ consecutive integers. None of the above.
answered
Jul 31, 2018
in
Algorithms

9.7k
views
gate20141
algorithms
timecomplexity
normal
+1
vote
24
GATE200860
What is printed by the following C program? int f(int x, int *py, int **ppz) { int y, z; **ppz += 1; z = **ppz; // corrected z = *ppz; to z = **ppz; *py += 2; y = *py; x += 3; return x+y+z; } void main() { int c, *b, **a; c = 4; b = &c; a = &b; printf("%d", f(c, b, a)); } $18$ $19$ $21$ $22$
answered
Jul 30, 2018
in
Programming

4.3k
views
gate2008
programming
programminginc
normal
0
votes
25
GATE2007IT31
Consider the C program given below : #include <stdio.h> int main () { int sum = 0, maxsum = 0, i, n = 6; int a [] = {2, 2, 1, 3, 4, 2}; for (i = 0; i < n; i++) { if (i == 0  a [i] < 0  a [i] < a [i  1]) ... [i]; } if (sum > maxsum) maxsum = sum ; printf ("%d\n", maxsum); } What is the value printed out when this program is executed? $9$ $8$ $7$ $6$
answered
Jul 30, 2018
in
Programming

2.9k
views
gate2007it
programming
programminginc
normal
+4
votes
26
GATE2014341
Consider the pseudocode given below. The function $DoSomething()$ takes as argument a pointer to the root of an arbitrary tree represented by the $leftMostChildrightSibling$ representation. Each node of the tree is of type $treeNode$. typedef struct treeNode* treeptr; ... tree. height of the tree. number of nodes without a right sibling in the tree. number of leaf nodes in the tree
answered
Jul 24, 2018
in
DS

5.6k
views
gate20143
datastructures
trees
normal
0
votes
27
If the default subnet mask for a N/W is 255.255.255.0 , and if M bits are borrowed what is supernet mask ?
answered
Apr 23, 2018
in
Computer Networks

181
views
computernetworks
+2
votes
28
Self doubt
What is the difference between Performance, Throughput ,Efficiency and speedup??
answered
Mar 27, 2018
in
CO and Architecture

60
views
computerarchitecture
0
votes
29
Gate 2017
L1={wstarts with a and ends with b} L2={wstarts with b and ends with a} then L1 ⋂ L2 will be: 1. Finite 2.CFL but not regular 3.none of the above.
answered
Feb 11, 2017
in
Theory of Computation

424
views
+4
votes
30
ISRO201647
A system has 3 processes sharing 4 resources. If each process needs a maximum of 2 units, then Deadlock can never occur Deadlock may occur Deadlock has to occur None of these
answered
Jul 4, 2016
in
Operating System

6k
views
operatingsystem
resourceallocation
isro2016
50,741
questions
57,244
answers
198,019
comments
104,611
users