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Recent activity by SeemaTanwar

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MadeEasy Test Series: Complier Design - Intermediate Code
someone please share detailed rules for this along with solution- would be of great help. and we usually dont take start and end state- arent they extra here? coz count comes different
someone please share detailed rules for this along with solution- would be of great help.and we usually dont take start and end state- arent they extra here? coz count co...
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Doubt -OS process scheduling
If arrival time of a process is same as the end time of quantum slice for a process in round robin schedule then in what order we must place the processes in ready queue?
If arrival time of a process is same as the end time of quantum slice for a process in round robin schedule then in what order we must place the processes in ready queue?...
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avl tree-AAI exam
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Leaky Bucket
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P&C examples : finding no of ways
The number of ways can 10 balls be chosen from an urn containing 10 identical green balls , 5 identical yellow balls and 3 identical blue balls are_______ .
The number of ways can 10 balls be chosen from an urn containing 10 identical green balls , 5 identical yellow balls and 3 identical blue balls are_______ .
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Made Easy test series
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clock cycles to access ALU and Register in Base Index addressing mOde
How many cycles will be required to fetch an operand if we are using "BASE INDEX' addressing mode, and ALU computation takes 2 cycles, register reference takes 1 cycle and memory reference takes 4 cycles each respectively ?
How many cycles will be required to fetch an operand if we are using "BASE INDEX' addressing mode, and ALU computation takes 2 cycles, register reference takes 1 cycle an...
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shift register
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cache hit latency computation
Consider 32 KB 4-way set associative cache with 32 byte block size. CPU generates 32 bits physical address . A 4 to1 multiplexer has a latency of 1 ns while a k bit comparator has a latency of 2k ns. The hit latency of the cache organization is?
Consider 32 KB 4-way set associative cache with 32 byte block size. CPU generates 32 bits physical address . A 4 to1multiplexer has a latency of 1 ns while a k bit compar...
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hit ratio computation
Consider a 4-way set associative cache that has 8 lines,with perfect LRU cache replacement and supports a block size of 16 bytes. For the following memory access pattern (shown as byte addresses), find the hit ratio? 3, 5, 6, 21, 32, 14, 5, 10, 11, 12 ?
Consider a 4-way set associative cache that has 8 lines,with perfect LRU cache replacement and supports a block size of16 bytes.For the following memory access pattern (s...
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Ace test series question on scheduling policy
which scheduling policy is starvation free? A) LIFO B) FIFO C) SJF D)PRIORITY
which scheduling policy is starvation free?A) LIFOB) FIFOC) SJFD)PRIORITY
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Round Robin scheduling policy
The I/O wait percentage p of a process is the percentage of time the process wait for an IO to completion when executed in a monoprogramming environment . on a system using round robin with n process ,all having same IO . what percentage of time cpu will be idle in term of (p) ?
The I/O wait percentage p of a process is the percentage of time theprocess wait for an IO to completion when executed in amonoprogramming environment . on a system using...
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Test series question............
In a 6 bit ripple counter the MOD of up counting is 14, then MOD of down counting is?
In a 6 bit ripple counter the MOD of up counting is 14, then MOD of down counting is?
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MP481 Review Problems Turing Machines and (Un)Decidability Luay K. Nakhleh
L1={<M>|M is a TM and |L(M)|<=3} L2={<M>|M is a TM and |L(M)|>=3} L3={<M>|M is a TM and L(M) is finite} How can we judge which language is rec, R. E or not R. E?
L1={<M>|M is a TM and |L(M)|<=3}L2={<M>|M is a TM and |L(M)|>=3}L3={<M>|M is a TM and L(M) is finite}How can we judge which language is rec, R. E or not R. E?
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decidability 
Decidability of M is a TM and L(M) is a regular language ?
Decidability of M is a TM and L(M) is a regular language ?