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Recent activity by Shubhanshu
0
answers
1
#Graphs #Self_Doubt #Connectivity
What is a biconnected componenet?Does it always include V-V’ where V’ represent the set of articulation points of a graph G?
What is a biconnected componenet?Does it always include V-V’ where V’ represent the set of articulation points of a graph G?
391
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commented
Feb 17, 2023
Graph Theory
graph-theory
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0
answers
2
Cross product of dfa
The below question is from test series. In the below question I think option B will be correct and C will not be correct. (If the image is appearing too small and blur please open the image on new tab for proper visibility) Following is the counter example for option C. ... D1 x D2 i.e (q1, q2); q1 is final state of D1 and q2 is final state of D2. Is my justification correct?
The below question is from test series.In the below question I think option B will be correct and C will not be correct. (If the image is appearing too small and blur ple...
349
views
commented
Nov 8, 2022
Theory of Computation
theory-of-computation
regular-language
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1
answer
3
SPU Scheduling
What is the correct sequence of the functions -Scheduling, dispatching, and context switching.
What is the correct sequence of the functions -Scheduling, dispatching, and context switching.
1.7k
views
answer selected
Nov 5, 2022
Operating System
operating-system
process-scheduling
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2
answers
4
Kenneth Rosen Edition 7 Exercise 8.3 Question 14 (Page No. 535)
Suppose that there are $n = 2^{k}$ teams in an elimination tournament, where there are $\frac{n}{2}$ games in the first round, with the $\frac{n}{2} = 2^{k-1}$ winners playing in the second round, and so on. Develop a recurrence relation for the number of rounds in the tournament.
Suppose that there are $n = 2^{k}$ teams in an elimination tournament, where there are $\frac{n}{2}$ games in the first round, with the $\frac{n}{2} = 2^{k-1}$ winners pl...
1.8k
views
edited
May 15, 2020
Combinatory
kenneth-rosen
discrete-mathematics
counting
recurrence-relation
descriptive
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1
answer
5
Discrete mathematics #TEST_BOOK
I Have doubt about the language. Is it asking about the sum of elements if we make the GBL set for the given lattice .
I Have doubt about the language. Is it asking about the sum of elements if we make the GBL set for the given lattice .
475
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commented
May 20, 2019
Set Theory & Algebra
discrete
lattice
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0
answers
6
Ullman (TOC) Edition 3 Exercise 1.7 Problem 1.1 (Page No. 35)
Find in the list below the expression that is the contrapositive of $A$ $AND$ $(NOT$ $B)\rightarrow C$ $OR$ $(NOT$ $D).$ Note: the hypothesis and conclusion of the choices in the list below may have some simple logical rules applied to them, in order to simplify the expression.
Find in the list below the expression that is the contrapositive of $A$ $AND$ $(NOT$ $B)\rightarrow C$ $OR$ $(NOT$ $D).$Note: the hypothesis and conclusion of the choices...
196
views
commented
Apr 2, 2019
Theory of Computation
ullman
theory-of-computation
descriptive
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3
answers
7
ISI2015-MMA-92
Consider the group $G=\begin{Bmatrix} \begin{pmatrix} a & b \\ 0 & a^{-1} \end{pmatrix} : a,b \in \mathbb{R}, \: a>0 \end{Bmatrix}$ ... is of finite order $N$ is a normal subgroup and the quotient group is isomorphic to $\mathbb{R}^+$ (the group of positive reals with multiplication).
Consider the group $$G=\begin{Bmatrix} \begin{pmatrix} a & b \\ 0 & a^{-1} \end{pmatrix} : a,b \in \mathbb{R}, \: a>0 \end{Bmatrix}$$ with usual matrix multiplication. Le...
1.4k
views
commented
Mar 7, 2019
Set Theory & Algebra
isi2015-mma
group-theory
subgroups
normal
non-gate
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4
answers
8
Fork (ACE)
main() { if(fork()>=0) { printf("*"); if(fork()==0) { printf("*"); } else{ //do nothing } printf("*"); } How many number of times “*” will be printed?
main() { if(fork()>=0) { printf("*"); if(fork()==0) { printf("*"); } else{ //do nothing } printf("*"); }How many number of times “*” will be printed?
3.3k
views
commented
Feb 27, 2019
Operating System
fork-system-call
operating-system
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0
answers
9
Networks by Fourozon
I have just started reading "Data communication and networking by Forouzan", I can't understand which chapters and sub-chapters are important.Please help.
I have just started reading "Data communication and networking by Forouzan", I can't understand which chapters and sub-chapters are important.Please help.
1.7k
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commented
Feb 8, 2019
11
answers
10
GATE CSE 2019 | Question: 45
A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept ... for the memory system when the program running on the processor issues a series of read operations is ______$\times 10^6$ bytes/sec.
A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a ...
20.5k
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commented
Feb 7, 2019
CO and Architecture
gatecse-2019
numerical-answers
co-and-architecture
cache-memory
2-marks
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4
answers
11
GATE CSE 2019 | Question: 3
Which one of the following kinds of derivation is used by LR parsers? Leftmost Leftmost in reverse Rightmost Rightmost in reverse
Which one of the following kinds of derivation is used by LR parsers?LeftmostLeftmost in reverseRightmostRightmost in reverse
9.6k
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commented
Feb 7, 2019
Compiler Design
gatecse-2019
compiler-design
parsing
1-mark
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5
answers
12
GATE CSE 2019 | Question: 2
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has $16$ address lines denoted by $A_{15}$ to $A_0$. What is the range of address (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal? C800 to CFFF CA00 to CAFF C800 to C8FF DA00 to DFFF
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has $16$ address lines denoted by $A_{15}$ to $A_0$....
12.7k
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commented
Feb 7, 2019
CO and Architecture
gatecse-2019
co-and-architecture
dram
1-mark
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8
answers
13
GATE CSE 2019 | Question: 1
A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses ... $0$ bits $28$ bits and $4$ bits $24$ bits and $4$ bits $28$ bits and $0$ bits
A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bi...
17.9k
views
commented
Feb 7, 2019
CO and Architecture
gatecse-2019
co-and-architecture
cache-memory
normal
1-mark
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3
answers
14
GATE CSE 2019 | Question: 14
Which one of the following statements is NOT correct about the B+ tree data structure used for creating an index of a relational database table? B+ Tree is a height-balanced tree Non-leaf nodes have pointers to data records Key values in each node are kept in sorted order Each leaf node has a pointer to the next leaf node
Which one of the following statements is NOT correct about the B+ tree data structure used for creating an index of a relational database table?B+ Tree is a height-balanc...
10.5k
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commented
Feb 7, 2019
Databases
gatecse-2019
databases
b-tree
1-mark
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1
answer
15
Digital Logic
355
views
answer selected
Feb 7, 2019
0
answers
16
SELF DOUBT
what is (120)base 10=( ? )base 64 ??
what is (120)base 10=( ? )base 64 ??
344
views
commented
Feb 4, 2019
Digital Logic
digital-logic
number-system
number-representation
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1
answer
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ME adv mock
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size ... words. The speed up of processor is achieved in dealing with average read miss after increasing the line size is_____ (Upto 2 decimal places)
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor ...
871
views
commented
Feb 1, 2019
CO and Architecture
co-and-architecture
cache-memory
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1
answer
18
Recurrence Relation
$T(n) = 2T(\sqrt{n}) + n$
$T(n) = 2T(\sqrt{n}) + n$
1.1k
views
answer selected
Feb 1, 2019
Algorithms
algorithms
time-complexity
recurrence-relation
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0
answers
19
Can Merge Sort Time Complexity be O(n^2) in any condition?
1.4k
views
commented
Feb 1, 2019
Algorithms
algorithms
time-complexity
sorting
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1
answer
20
ME adv Test
Suppose that host A is connected to a router R1, R1 is connected to another router R2 and R2 is connected to host B. Suppose that a TCP message that contains 900 bytes of data and 20 bytes of TCP header is passed to the IP layer at host A for delivery to B. Assume ... Offset=63 LENGTH=460; DF=0;MF=0;Offset=60. (Given ans is C can anyone help with this question whether ans is D or C? )
Suppose that host A is connected to a router R1, R1 is connected to another router R2 and R2 is connected to host B. Suppose that a TCP message that contains 900 bytes of...
719
views
commented
Feb 1, 2019
Computer Networks
computer-networks
fragmentation
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1
answer
21
Self doubt- Min no of NOR gates
What is the minimum number of 2 input NOR gates required to realise: F(A,B,C) = (A'+B')(B'+C')(C'+A') Case 1- Compliments of A,B,C are not available Case 2- Compliments of A,B,C are available
What is the minimum number of 2 input NOR gates required to realise:F(A,B,C) = (A'+B')(B'+C')(C'+A')Case 1- Compliments of A,B,C are not availableCase 2- Compliments of A...
733
views
commented
Feb 1, 2019
0
answers
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SelfDoubt
Checking for Euler Path i.A graph has Euler path if exactly two vertices is of odd degree. if a graph have euler circuit=>all vertices even degree=>euler circuit which already cover euler path. am i correct? i is necessary and sufficient condition? So for ... check either 1.Euler Circuit or 2.Exactly two odd degree then it will have euler path but not euler circuit. is it correct?
Checking for Euler Pathi.A graph has Euler path if exactly two vertices is of odd degree.if a graph have euler circuit=>all vertices even degree=>euler circuit which alre...
487
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commented
Jan 31, 2019
0
answers
23
GeeksforGeeks
Let G be a graph with no isolated vertices, and let M be a maximum matching of G. For each vertex v not saturated by M, choose an edge incident to v. Let T be the set of all the chosen edges, and let L = M ∪ T. Which of the following option is TRUE? A L is always ... G. B L is always a minimum edge cover of G. C Both (A) and (B) D Neither (A) nor (B) Can anyone pls help solving this?
Let G be a graph with no isolated vertices, and let M be a maximum matching of G. For each vertex v not saturated by M, choose an edge incident to v. Let T be the set of ...
1.5k
views
commented
Jan 30, 2019
Graph Theory
graph-matching
discrete-mathematics
graph-theory
test-series
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0
answers
24
MadeEasy Test Series 2019: Computer Networks - Congestion Control
Consider a TCP connection using the multiplicative additive congestion control algorithm where the window size is 1 MSS and the threshold is 32 MSS. At the $8^{th}$ transmission timeout occurs and enters in the congestion detection ... transmission. So we have to take the window size after the 12 RTTs right and not at 12th RTT?
Consider a TCP connection using the multiplicative additive congestion control algorithm where the window size is 1 MSS and the threshold is 32 MSS. At the $8^{th}$ trans...
1.9k
views
commented
Jan 30, 2019
Computer Networks
computer-networks
congestion-control
made-easy-test-series
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0
answers
25
Self dout
Which phase of the compiler detects the error? #include<stdio.h> int main() { printf(“%d”,2..3); return 0; } I think lexical analyzer am i correct?
Which phase of the compiler detects the error?#include<stdio.h>int main(){printf(“%d”,2..3);return 0;}I think lexical analyzer am i correct?
461
views
commented
Jan 30, 2019
Compiler Design
compiler-design
error-detection
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–
2
answers
26
Made Easy Test Series
b = b + c d = b + d b = b – d e = d + b The minimum number of nodes and edges present in the DAG representation of above basic block respectively are ? 4 and 5 5 and 4 6 and 6 6 and 7
b = b + cd = b + db = b – de = d + bThe minimum number of nodes and edges present in the DAG representation of above basic block respectively are ?4 and 55 and 46 and 6...
2.4k
views
commented
Jan 27, 2019
Compiler Design
compiler-design
code-optimization
directed-acyclic-graph
made-easy-test-series
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0
answers
27
MadeEasy Subject Test 2019: Digital Logic - Digital Counter
Consider the circuit given below. Assume initially flipflops are in reset state. What will be the mod of above digital circuit?
Consider the circuit given below. Assume initially flipflops are in reset state. What will be the mod of above digital circuit?
471
views
commented
Jan 27, 2019
Digital Logic
digital-logic
digital-counter
made-easy-test-series
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0
answers
28
made easy test series
409
views
commented
Jan 27, 2019
1
answer
29
Quora
In a directed graph, a path is called special if every sub-path of the path is shortest path. Sub-path of a path P means every path in the path P, except P. A. Every shortest path is special B. Every special path is shortest
In a directed graph, a path is called special if every sub-path of the path is shortest path. Sub-path of a path P means every path in the path P, except P.A. Every short...
321
views
commented
Jan 25, 2019
0
answers
30
fork() system call
497
views
commented
Jan 25, 2019
Operating System
unix
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