# Questions by Somoshree Datta 5

1
Consider the following statements about relation R: S1: If a relation R is in 3NF but not in BCNF, then relation R must consist proper subset of candidate key determines proper subset of some other candidate key. S2: If a relation R is in 3NF but not BCNF, then relation R must ... Which of the following statements is/are correct? (a) Both S1 and S2 (b) Only S1 © Only S2 (d) None of the above
2
In the given network system, station A needs to send a payload of 1600B from its network layer to station B. If fragmentation is done, then the actual data size to be transmitted is?
3
Consider the following language:? L= {w | w $\epsilon$ {0,1}* , w has equal number of occurrences of ‘001’ and ‘010’} Is L regular? If so, please provide a DFA for L.
4
Consider the following statements: S1: In ethernet, jamming signal ensure that all nodes using the channel are aware for their transmission(s) failed. S2: Bit stuffing ensures that all frames are of the same size. Which of the following is true? (a) Only S1 (b) Only S2 © Both S1 and S2 (d) Neither S1 nor S2
5
Match List-I and List-II and select the correct answer using the codes given below the lists as per the deadlock prevention scheme: List-I List-II (a) Belady’s anomaly 1. Local replacement Algorithm (b) Lazy Swapper 2. FIFO page replacement © Counters 3. Demand paging (d) Thrashing 4. Least recently used page replacement A B C D (a) 1 3 2 4 (b) 2 3 4 1 © 2 1 4 3 (d) 1 4 2 2
6
Consider the following predicates: S(x): x is a student GATE(x,y): x has written gate in stream y. Which of the following is equivalent predicate logic for the statement : There doesnt exist a student who has written GATE in every stream. (a)$\exists y\exists x[S(x)\Lambda \sim GATE(x,y)]$ ... $\exists y\exists x[\sim S(x)\Lambda \sim GATE(x,y)]$
7
The output of the program if dynamic scoping is used__?
8
Consider a disk drive with the following specifications. 16 surfaces, 128 tracks / surfaces, 256 sectors / track, 512 B / sector, rotations speed 3600 rpm. The disk is operated in cycle stealing mode whereby whenever one byte word is ready it is sent to ... memory in each DMA cycle. Memory cycle time is 50microsec. The maximum percentage of time the CPU gets blocked during DMA operation is______?
9
10
1 vote
11
Consider a relation R(A,B,C,D,E) and functional dependencies: F= (AC->B, C->D, A->E, C->B) Relation R is decomposed into R1(A,B,C) and R2(C,D), then which of the following is correct about the decomposition? (a) Lossless and dependency preserving (b) Lossy and dependency preserving © Lossless and not dependency preserving (d) Not Lossless and not dependency preserving
12
Match List I (Characteristic) with List II (Processor Architechture) and select the correct answer using the code given below the lists: List I List II (a) Micro-code for several instructions 1. Both RISC and CISC (b) Lack of indirect addressing 2. CISC only © Presence of on-chip cache 3. Neither RISC nor CISC (d) ... compiler 4. RISC only A B C D (a) 2 4 1 3 (b)1 3 2 4 (c)2 3 1 4 (d)1 4 2 3
1 vote
13
Given a sorted array of distinct integers A[1,2,3,..,n], the tightest upper bound to check the existence of any index i for which A[i]= i is equal to O($n^{a}log^{b}n)$. Then a+10b is equal to ___?
1 vote
14
Assertion(A): The DMA technique is more efficient than the interrupt-driven technique for high volume I/O data transfer. Reason(R): The DMA technique doesnt make use of the interrupt mechanism. (a) Both A and R are true and R is the correct explanation of A. (b) Both A and R are true but R is not the correct explanation of A. © A is true but R is false. (d) A is false but R is true.
15
In the following question https://gateoverflow.in/192674/made-easy-test-series Why has block offset being considered as 4bits? It is mentioned in the question that memory is word addressable data words are word-addressable. Then why are we not computing the bits reserved for each field in terms of words rather than bytes? Shouldnt the block offset be 2 bits as 4 words are present in a block?
16
Consider a single level cache with an access time of 2.5ns, a line of 64B and a hit ratio of 0.95. Main memory uses a block transfer capability that has a first word i.e. 4B access time of 50ns and after that 5ns for each word access. If cache waits until block is copied from MM to the cache and then access from cache,the access time is________(in ns) (upto 3 decimal places)
17
In this question, https://gateoverflow.in/69709/pipelining Kapil Sir had commented that we can do split phase access between memory access(MA) stage and execute(EX) stage of a pipeline..but how is split phase access possible here? As far as i know, memory access ... in this link https://gateoverflow.in/252781/operand-forwarding Can we use split phase access between MA and EX stage in this case?