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1

GATE CSE 2006 | Question: 68
Consider the relation enrolled (student, course) in which (student, course) is the primary key, and the relation paid (student, amount) where student is the primary key. Assume no null values and no foreign keys or integrity constraints. ... strictly fewer rows than Query$2$ There exist databases for which Query$4$ will encounter an integrity violation at runtime

commented in Databases Nov 11, 2018

16.2k views

6 answers

2

GATE CSE 2012 | Question: 15
Which of the following statements are TRUE about an SQL query? P : An SQL query can contain a HAVING clause even if it does not have a GROUP BY clause Q : An SQL query can contain a HAVING clause only if it has a GROUP BY clause R : All attributes used ... Not all attributes used in the GROUP BY clause need to appear in the SELECT clause P and R P and S Q and R Q and S

commented in Databases Nov 11, 2018

35.1k views

7 answers

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GATE CSE 2018 | Question: 51
A processor has $16$ integer registers $\text{(R0, R1}, \ldots ,\text{ R15)}$ and $64$ floating point registers $\text{(F0, F1}, \ldots , \text{F63)}.$ It uses a $2\text{- byte}$ instruction format. There are four categories of ... $\text{(1F)}.$ The maximum value of $\text{N}$ is _________.

commented in CO and Architecture Apr 17, 2018

19.8k views

3 answers

4

ISRO2014-48
A frame buffer array is addressed in row major order for a monitor with pixel locations starting from $(0,0)$ and ending with $(100,100).$ What is address of the pixel $(6,10)?$ Assume one bit storage per pixel and starting pixel location is at $0.$ $1016$ $1006$ $610$ $616$

commented in Computer Graphics Apr 15, 2018

7.6k views

2 answers

5

ISRO2011-37
Find the memory address of the next instruction executed by the microprocessor $(8086),$ when operated in real mode for $\textsf{CS=1000}$ and $\textsf{IP=E000}$ $\textsf{10E00}$ $\textsf{1E000}$ $\textsf{F000}$ $\textsf{1000E}$

commented in CO and Architecture Apr 11, 2018

6.7k views

2 answers

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GATE CSE 2018 | Question: 6
Let $N$ be an NFA with $n$ states. Let $k$ be the number of states of a minimal DFA which is equivalent to $N$. Which one of the following is necessarily true? $k \geq 2^n$ $k \geq n$ $k \leq n^2$ $k \leq 2^n$

commented in Theory of Computation Feb 14, 2018

8.4k views

0 answers

7

Self doubt on Ethernet LAN
Are the below formulas for correct w.r.t ethernet LAN? efficiency : PD = propagation delay TD = transmission delay L = frame size $\eta =\frac{1}{1 + 6.44(\frac{ pd }{ td })}$ throughput: $= \frac{L}{RTT}$ If they are wrong please provide correct ones.

commented in Computer Networks Feb 1, 2018

617 views

0 answers

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Self Doubt Ethernet
When do we use $\eta = 1/(1+6.44a)$ and when do we use $\eta = 1/(1+2a)$ {a = pd/td}. I am very confused between efficiency, throughput, utilization...please help! {Pd = Propagation delay, td = transmission delay}

commented in Computer Networks Feb 1, 2018

442 views

5 answers

9

Formula for calculating efficiency of ethernet
What formula to use for calculating efficiency of ethernet is it $\frac{1}{1+6.44a}$ or $\frac{1}{1+5.44a}$ or $\frac{1}{1+5a}$ I saw three versions for calculating the same thing in different places. I want to know which one is correct.

commented in Computer Networks Feb 1, 2018

14.8k views

2 answers

10

Understanding How to Identify Number of Tables for ER Diagram
Doubts - 1) When a ER diagram is given and no cardinalities are provided. How to determine relationship type 1:1 or 1:N or M:N ? Generally in such ER diagrams arrows are given. Referring to this article where arrow is a ... ternary relation? Is there a relationship between E3 and E2 via R1 in below example ? Question 1 - Question 2 -

commented in Databases Jan 29, 2018

5.7k views

0 answers

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MadeEasy Full Length Test 2019: Databases - Er Diagram
Find minimum number of tables needed? Answer : (3) Can anyone please explain the answer and how to approach such complex er diagrams?

commented in Databases Jan 29, 2018

718 views

0 answers

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Self Doubt : Number of tables for an ER Diagram
Plz tell whether this formula is correct? Number of tables for an ER Diagram = [Number of Entities+Number of Multivalued Attributes + Number of M:N Cardinality Ratios(with no Total Participation on both entities)]

commented in Databases Jan 29, 2018

227 views

1 answer

13

MadeEasy Test Series 2018: Algorithms - Dynamic Programming
The number of balance parenthesis possible with 5-pairs of parenthesis _________. [ Assume ( ) and (( )) is balance parenthesis but not ) ( ]

asked in Algorithms Jan 29, 2018

1.8k views

3 answers

14

What is the number of states in the minimal DFA with input symbols {0,1,2} where 2nd last symbol is 1?

commented in Theory of Computation Jan 24, 2018

2.9k views

1 answer

15

Number of States in minimal DFA
How many states will have the minimal DFA accepting the language L={w|wϵ{0,1}* and contains atleast one 0 and two 1's} a) 6 b)7 c)8 d)12

commented in Theory of Computation Jan 24, 2018

548 views

2 answers

16

Number of states in a minimal DFA construction
Suppose L is a regular language of all a's and b's where the number of a's is divisible by m and the number of b's is divisible by n. If M is the minimal DFA accepting language L, then what is the number of states in M ? Is it nm or (n+1)(m+1) ?

commented in Theory of Computation Jan 24, 2018

1.5k views

1 answer

17

#test_series
let L be a set of binary string whose integer equivalent is congruent to 10 (mod 16) Then minimal DFA that accept L contains how many states ? plz explain

answered in Theory of Computation Jan 23, 2018

295 views

10 answers

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GATE CSE 2009 | Question: 30
Consider a system with $4$ types of resources $R1$ ($3$ units), $R2$ ($2$ units), $R3$ ($3$ units), $R4$ ($2$ units). A non-preemptive resource allocation policy is used. At any given instance, a request is not entertained if it cannot be ... deadlock Only $P1$ and $P2$ will be in deadlock Only $P1$ and $P3$ will be in deadlock All three processes will be in deadlock

commented in Operating System Jan 23, 2018

28.5k views

3 answers

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GATE CSE 2010 | Question: 33
A $5-$stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take $1$ clock cycle each for any instruction. The PO stage takes $1$ clock cycle for ... $13$ $15$ $17$ $19$

commented in CO and Architecture Jan 23, 2018

18.2k views

5 answers

20

number of schedules conflict equivalent schedule
Consider the following schedule: S : w1(A) w1(B) r2(A) w2(B) r3(A) w3(B) The number of schedules conflict equivalent are __________ .

commented in Databases Jan 23, 2018

5.8k views

0 answers

21

Rice's Theorem
What is monotonic and non-monotonic property. Please explain the second postulate of Rice's Theorem.

asked in Theory of Computation Jan 23, 2018

321 views

0 answers

22

MadeEasy Test Series 2018: Algorithms - Asymptotic Notations
Let f (n) = Ο(n), g(n) = Ω(n) and h(n) = θ(n). Then g(n) + f(n).h(n) is ______ A.) Ω(n) B.) θ(n2) C.) Ω(n2) D.) θ(n) How to do these type of questions ?

commented in Algorithms Jan 23, 2018

492 views

4 answers

23

GATE CSE 2003 | Question: 11
Consider an array multiplier for multiplying two $n$ bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is $\Theta(1)$ $\Theta(\log n)$ $\Theta(n)$ $\Theta(n^2)$

commented in Digital Logic Jan 22, 2018

12.6k views

1 answer

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MadeEasy Test Series 2018: Theory of Computation - Identify Class Language
a) Only L1 is correct b)Only L2 is correct c)Both L1 and L2 are correct d)None of L1 and L2 is correct My question is: What is meant by prefix of string? And how is L1 regular?

asked in Theory of Computation Jan 22, 2018

346 views

1 answer

25

Gateforum Test Series

commented in CO and Architecture Jan 20, 2018

411 views

4 answers

26

GATE CSE 1992 | Question: 02-i
The operation which is commutative but not associative is: AND OR EX-OR NAND

commented in Digital Logic Jan 19, 2018

5.1k views

1 answer

27

Memory access time
Suppose the time taken to write in cache is tc and time to write in main memory is tm. If write back policy is used, only the main memory is written and time taken is tm. But if write through is used, are the main memory and cache updated simultaneously (time taken would be tm) or serially (time taken would be tc + tm)?

asked in CO and Architecture Jan 18, 2018

540 views

4 answers

28

GATE CSE 2007 | Question: 37, ISRO2009-37
Consider a pipelined processor with the following four stages: IF: Instruction Fetch ID: Instruction Decode and Operand Fetch EX: Execute WB: Write Back The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX ... $ R5$-$R4} \\ \end{array}$ $7$ $8$ $10$ $14$

commented in CO and Architecture Jan 14, 2018

12.9k views

9 answers

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GATE CSE 2009 | Question: 28
Consider a $4$ stage pipeline processor. The number of cycles needed by the four instructions $I1, I2, I3, I4$ in stages $S1, S2, S3, S4$ ... the number of cycles needed to execute the following loop? For (i=1 to 2) {I1; I2; I3; I4;} $16$ $23$ $28$ $30$

commented in CO and Architecture Jan 13, 2018

26.9k views

4 answers

30

GATE CSE 2015 Set 3 | Question: 46
Consider a B+ tree in which the search key is $12$ $\text{bytes}$ long, block size is $1024$ $\text{bytes}$, record pointer is $10$ $\text{bytes}$ long and the block pointer is $8$ $\text{bytes}$ long. The maximum number of keys that can be accommodated in each non-leaf node of the tree is ______.

commented in Databases Jan 9, 2018

18.6k views