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Recent activity by abhijeet pandey

3 answers
1
Consider the 2 transactions T1: R(A) W(A) W(B) T2: R(A) W(A) R(B) W(B) How many view serializable schedules are possible which are not conflict serializable? (A) 0 (B) 1 (C) 2 (D) 3
commented Jan 5, 2018 in Databases 1.2k views
0 answers
2
Whether to count disk head movement during JUMP In CSCAN and CLOOK or not. I found 2 pdf's both are saying different things? http://www.cpp.edu/~kanluezhang/cs537/presentation/CS537-DiskScheduling-Rev.051915.pdf http://www4.comp.polyu.edu.hk/~csajaykr/myhome/teaching/eel358/ds.pdf
asked Jan 5, 2018 in Operating System 103 views
0 answers
3
Statement 1 : For every DCFL there exits a LR(0) or a LR(1) grammer. Statement 2 : For every DCFL there exits a LR(1) grammer. Which is true??
commented Dec 26, 2017 in Compiler Design 127 views
0 answers
4
Is 1's/2's complement valid only for negative numbers? If 2's complement of a number is 1111111111110101, then the number should be 0000000000001011. Then the decimal representation should be +11. But the answer is -11.
commented Dec 26, 2017 in Digital Logic 413 views
1 answer
5
Which of the following statement/s is/are false for the following language: $L = \{a^m b^n c^q \mid m = n \text{ or } n = q, m > 0, n > 0, q > 0\}$ S1: The language can be parsed by any LR(K) parsers for any value of K. S2: The language cannot be recognized by deterministic PDA. Only S2 Only S1 Both S1 and S2 Neither S1 nor S2
answer selected Dec 25, 2017 in Compiler Design 218 views
1 answer
6
Which of the following not a token of C program? a)1.02e+2 b)#define c)MAX d)123.33
answered Dec 24, 2017 in Compiler Design 376 views
1 answer
7
A system has CPU organized in the form of general register organization consisting of 16 registers, each storing 32 bit data. assume ALU have 35 operations . how many multiplexer are needed and what is the size of mux.
answered Dec 24, 2017 in CO and Architecture 89 views
4 answers
8
Suppose that a task makes extensive use of floating point operations with 40% of the time is consumed by floating point operations. With a new hardware design, the floating point module is speeded up by a factor of 4. What is the overall speedup? A. 1.05 B. 1.42 C. 2.5 D. 4 Please explain the little bit problem also.
answered Dec 23, 2017 in CO and Architecture 966 views
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