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Recent activity by aravind90
5
answers
1
GATE IT 2007 | Question: 7
Which of the following input sequences for a cross-coupled $R-S$ flip-flop realized with two $NAND$ gates may lead to an oscillation? $11, 00$ $01, 10$ $10, 01$ $00, 11$
Which of the following input sequences for a cross-coupled $R-S$ flip-flop realized with two $NAND$ gates may lead to an oscillation?$11, 00$$01, 10$$10, 01$$00, 11$
22.4k
views
answered
Nov 10, 2014
Digital Logic
gateit-2007
digital-logic
normal
flip-flop
+
–
6
answers
2
GATE CSE 1996 | Question: 2.25
A micro program control unit is required to generate a total of $25$ control signals. Assume that during any micro instruction, at most two control signals are active. Minimum number of bits required in the control word to generate the required control signals will be: $2$ $2.5$ $10$ $12$
A micro program control unit is required to generate a total of $25$ control signals. Assume that during any micro instruction, at most two control signals are active. Mi...
24.8k
views
answered
Oct 26, 2014
CO and Architecture
gate1996
co-and-architecture
microprogramming
normal
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9
answers
3
GATE CSE 2014 Set 1 | Question: 43
Consider a $6$-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time overhead of pipelining. When an application is executing on this $6$-stage pipeline, the speedup achieved with respect to non-pipelined execution if $25$% of the instructions incur $2$ pipeline stall cycles is ____________
Consider a $6$-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time overhead of pipelining. When an application is exec...
20.0k
views
answered
Oct 25, 2014
CO and Architecture
gatecse-2014-set1
co-and-architecture
pipelining
numerical-answers
normal
+
–
6
answers
4
GATE CSE 2014 Set 3 | Question: 44
The memory access time is $1$ nanosecond for a read operation with a hit in cache, $5$ nanoseconds for a read operation with a miss in cache, $2$ nanoseconds for a write operation with a hit in cache and $10$ nanoseconds for a write ... cache hit-ratio is $0.9$. The average memory access time (in nanoseconds) in executing the sequence of instructions is ______.
The memory access time is $1$ nanosecond for a read operation with a hit in cache, $5$ nanoseconds for a read operation with a miss in cache, $2$ nanoseconds for a write ...
24.0k
views
answered
Oct 25, 2014
CO and Architecture
gatecse-2014-set3
co-and-architecture
cache-memory
numerical-answers
normal
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