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+3
votes
1
Letters in boxes  combinations
Q .) The number of ways can 5 letter be put in 3 boxes A, B,C such that A has at least 2 letters. My approach: Number of ways to choose 2 letters out of 5 is 5C2. And for each such combination the remaining 3 letter have 3 choice. Therefore 5C2 * 3^3, but this is incorrect. Please point out the fault in my understanding and also the correct way to solve it
answered
Feb 1, 2019
in
Combinatory

113
views
combinatory
+3
votes
2
ME MOCK 4
Consider the following function: void madeeasy (int n) { if (n < 0) return; else { printf(n); madeeasy ( n); madeeasy (n  ); printf(n); } } The sum of all values printed by madeeasy (5)_______ (I am getting 12 but given answer is 52)
answered
Jan 31, 2019
in
Programming

395
views
programminginc
recursion
0
votes
3
Test series
Consider a system with main memory access time is 150ns and page fault service time is 5 microsecond if onepage fault generated for every 10^3 memory access then what is effective memory access time(in ns)?? The answer given is 154.85 and the answer I am getting is 4850.15 please verify someone
answered
Jan 31, 2019
in
CO and Architecture

45
views
+5
votes
4
MadeEasy Test Series 2019: CO & Architecture Cache Memory
Consider a nway cache with 'x blocks of 64 words each. The main memory of the system is having 8 million words. Size of the tag field is 16 bits and additional memory required for tags is 1024 bytes. What will be the values of n and x respectively? Answer 256 512
answered
Jan 30, 2019
in
CO and Architecture

347
views
coandarchitecture
cachememory
madeeasytestseries2019
madeeasytestseries
+5
votes
5
MadeEasy Test Series 2019: CO & Architecture  Cache Memory
A CPU cache is organized into 2 level cache L1 and L2 The penalty for L1 cache miss and L2 cache miss are 60 and 30 respectively for 1200 memory references The hit time of L1 and L2 are 5 and 10 clock cycles and penalty for L2 cache miss to main memory is 70 clock cycles. The average memory access time will be
answered
Jan 30, 2019
in
CO and Architecture

338
views
coandarchitecture
cachememory
madeeasytestseries2019
madeeasytestseries
+5
votes
6
MadeEasy Test Series
What is the number of seven digit integers possible with sum of the digits equal to 11 and formed by using the digits 1, 2 and 3 only?
answered
Jan 29, 2019
in
Combinatory

139
views
+3
votes
7
MadeEasy Subject Test 2019: Combinatory  Permutations And Combinations
Q.The number of ways, we can arrange 5 books in 3 shelves ________.
answered
Jan 29, 2019
in
Combinatory

619
views
discretemathematics
combinatory
madeeasytestseries2019
madeeasytestseries
+2
votes
8
Testbook Test Series: Operating System  File System
A file system with 300 GB uses a file descriptor with 8 direct block address. 1 indirect block address and 1 doubly indirect block address. The size of each disk block is 256 Bytes and the size of each disk block address is 16 Bytes. The maximum possible file size in this file system is? The answer given was 70KB. Thanks!
answered
Jan 28, 2019
in
Operating System

127
views
operatingsystem
filesystem
testbooktestseries
+2
votes
9
MadeEasy Test Series : Probability  Probability
A dice is tossed thrice. A success is getting ‘1 or 6' on a toss. Find the variance of number of successes _. Answer 0.66
answered
Jan 25, 2019
in
Probability

178
views
engineeringmathematics
probability
madeeasytestseries
+1
vote
10
Made Easy
A hypothetical 5 stage processor is designed in which branch is predicted at 3 stage and each stage takes 1 cycle to compute its task. If f is the probability of an instruction being a branch instruction then what is the value of F such that speed up is atleast 3?
answered
Jan 23, 2019
in
CO and Architecture

57
views
+1
vote
11
MadeEasy
A cyclic group O(G)=200 g be its generator O(g^x)=100 for some x.what is value of x? a.1 b.2 c.3 d.4 1 and 3 cant be possible as [order of generator equal to order of group] how to choose bw 2 and 4???
answered
Jan 22, 2019
in
Set Theory & Algebra

48
views
0
votes
12
flip flop : find mod of counter having presets as shown
answered
Jan 21, 2019
in
Digital Logic

148
views
digitallogic
flipflop
+3
votes
13
MadeEasy Test Series: Discrete Mathematics  Graph Thoery
The number of labelled subgraphs possible for the graph given below.
answered
Jan 20, 2019
in
Graph Theory

459
views
madeeasytestseries
discretemathematics
graphtheory
0
votes
14
MADE ESY MOCK 1
consider R(A,B,C,D,E) with FDs AB>C,C>D,D>B,D>E if number of keys in relation R is ‘a’ and the number of relation in 3NF decomposition is ‘b’ what is the value of ab? i am getting a=3,b=4 ab=1 am i correct?
answered
Jan 20, 2019
in
Databases

48
views
0
votes
15
Database
minimum no fo relation require for this ER diagram i am thinking 3 relation but given answer is______something else
answered
Jan 19, 2019
in
Databases

56
views
databases
0
votes
16
ME TEST SERIES QUESTION ON PIPELINE
answered
Jan 17, 2019
in
CO and Architecture

66
views
+2
votes
17
#combinatorics
How many ways the letters of the word “AABCCD” can be arranged such that, these neither begin with ‘A’ nor end with D ?
answered
Jan 15, 2019
in
Combinatory

87
views
combinatory
engineeringmathematics
+2
votes
18
METESTSERIESMOCK116
given a relation on R on the set A={1,2,3,4} in the form of matrix representation as , $M_R$=$\begin{bmatrix} 0 & 1 & 0 & 0\\ 0& 0& 1 &0 \\ 0& 0& 0 &1 \\ 0& 0& 0& 0 \end{bmatrix}$ Then the cardinality of the smallest equivalence relation on A which contains R is equal to answer given16
answered
Jan 13, 2019
in
Set Theory & Algebra

93
views
0
votes
19
Test series
L1= {w1w2 ∣ w1, w2 ∈ {0, 1}∗ and w1 ≠ w2} L2 = {ww ∣ w ∈ {0, 1}∗} Are the two languages compliment to each other? Is L2 compliment is CFL?
answered
Dec 23, 2018
in
Theory of Computation

31
views
0
votes
20
MadeEasy Test Series: CO & Architecture  Cache Memory
consider a CPU contains 2000 instructions, there are 80 misses in L1 cache and 40 misses in the L2 cache. Assume miss penalty from the L2 cache to memory is 200 clock cycles, the hit time of L2 cache is 30 clock cycles, the hit ... and there are 1.8 memory references per instruction, then average stall per instruction is 6.36 7.92 9.62 9.35
answered
Dec 18, 2018
in
CO and Architecture

189
views
madeeasytestseries
coandarchitecture
cachememory
+2
votes
21
MadeEasy Subject Test 2019: Computer Networks  Congestion Control
Consider an instance of TCP's Additive Increase Multiplicative Decrease (AIMD) algorithm where the window size at the start of slow start phase is 1 MSS and the threshold at the start is 1st transmission is 16 MSS. Assume TCP use ... after transmission of 7th packet . What is the congestion window size at the end of 14 RTT (in MSS)?
answered
Dec 1, 2018
in
Computer Networks

276
views
madeeasytestseries
computernetworks
congestioncontrol
+1
vote
22
Local Coaching
A cache is having 60% hit ratio. Cache access time is 30 ns and main memory access time is 100 ns. What is the average access time for reading? My doubt is whether to assume cache and main memory to be hierarchically connected or directly connected to the processor when nothing is given? If assumed ... , ans = 0.6(30) + 0.4(30+100). If assumed to be direct, ans = 0.6(30) + 0.4(100).
answered
Nov 27, 2018
in
CO and Architecture

69
views
coap
cachememory
0
votes
23
Gate 2018 College Chances
Hi ... My gate score is 691 (53.7/100) and AIR 687 (General Category).. Could you please help me in knowing the best possible option in Mtech/MS for computer science.. Any chances to get into any IITs ???
answered
Apr 11, 2018
in
Written Exam

293
views
52,345
questions
60,484
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201,813
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95,290
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