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Answers by d3ba
76
votes
1
GATE CSE 2020 | Question: 54
Consider a database implemented using $\text{B+}$ tree for file indexing and installed on a disk drive with block size of $\text{4 KB}$. The size of search key is $\text{12 bytes}$ ... that each record fits into one disk block. The minimum number of disk accesses required to retrieve any record in the database is _______
Consider a database implemented using $\text{B+}$ tree for file indexing and installed on a disk drive with block size of $\text{4 KB}$. The size of search key is $\text{...
22.3k
views
answered
Feb 12, 2020
Databases
gatecse-2020
numerical-answers
databases
b-tree
indexing
2-marks
+
–
110
votes
2
GATE CSE 2020 | Question: 53
Consider a paging system that uses $1$-level page table residing in main memory and a $\textsf{TLB}$ for address translation. Each main memory access takes $100$ ns and $\textsf{TLB}$ lookup takes $20$ ns. Each page transfer to/from the disk ... $1$ decimal places) is ___________
Consider a paging system that uses $1$-level page table residing in main memory and a $\textsf{TLB}$ for address translation. Each main memory access takes $100$ ns and $...
45.0k
views
answered
Feb 12, 2020
Operating System
gatecse-2020
numerical-answers
operating-system
virtual-memory
2-marks
+
–
49
votes
3
GATE CSE 2020 | Question: 44
A processor has $64$ registers and uses $16$-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a $4$-bit immediate value. Each R-type instruction ... two register names. If there are $8$ distinct I-type opcodes, then the maximum number of distinct R-type opcodes is _______.
A processor has $64$ registers and uses $16$-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a re...
28.6k
views
answered
Feb 12, 2020
CO and Architecture
gatecse-2020
co-and-architecture
numerical-answers
instruction-format
machine-instruction
2-marks
+
–
31
votes
4
GATE CSE 2020 | Question: 43
Consider a non-pipelined processor operating at $2.5$ GHz. It takes $5$ clock cycles to complete an instruction. You are going to make a $5$- stage pipeline out of this processor. Overheads associated with pipelining force you to ... , the speedup achieved by the pipelined processor over the non-pipelined processor (round off to $2$ decimal places) is_____________.
Consider a non-pipelined processor operating at $2.5$ GHz. It takes $5$ clock cycles to complete an instruction. You are going to make a $5$- stage pipeline out of this p...
16.3k
views
answered
Feb 12, 2020
CO and Architecture
gatecse-2020
numerical-answers
co-and-architecture
pipelining
2-marks
+
–
3
votes
5
GATE CSE 2020 | Question: 42
The number of permutations of the characters in LILAC so that no character appears in its original position, if the two L’s are indistinguishable, is ______.
The number of permutations of the characters in LILAC so that no character appears in its original position, if the two L’s are indistinguishable, is ______.
16.3k
views
answered
Feb 12, 2020
Combinatory
gatecse-2020
numerical-answers
combinatory
2-marks
+
–
43
votes
6
GATE CSE 2020 | Question: 41
In a balanced binary search tree with $n$ elements, what is the worst case time complexity of reporting all elements in range $[a,b]$? Assume that the number of reported elements is $k$. $\Theta (\log n)$ $\Theta (\log n +k)$ $\Theta (k \log n)$ $\Theta ( n \log k)$
In a balanced binary search tree with $n$ elements, what is the worst case time complexity of reporting all elements in range $[a,b]$? Assume that the number of reported ...
21.5k
views
answered
Feb 12, 2020
DS
gatecse-2020
data-structures
binary-search-tree
2-marks
+
–
14
votes
7
GATE CSE 2020 | Question: 37
Consider a schedule of transactions $T_1$ and $T_2$ ...
Consider a schedule of transactions $T_1$ and $T_2$:$\begin{array}{|c|c|c|c|c|c|c|c|c|c|c|} \hline T_1 & RA & & & RC & & WD & & WB & \text{Commit} & \\ \hline T_2 & & R...
11.7k
views
answered
Feb 12, 2020
Databases
gatecse-2020
databases
transaction-and-concurrency
2-marks
+
–
16
votes
8
GATE IT 2007 | Question: 63
A group of $15$ routers is interconnected in a centralized complete binary tree with a router at each tree node. Router $i$ communicates with router $j$ by sending a message to the root of the tree. The root then sends the message back down to router $j$ ... mean number of hops per message, assuming all possible router pairs are equally likely is $3$ $4.26$ $4.53$ $5.26$
A group of $15$ routers is interconnected in a centralized complete binary tree with a router at each tree node. Router $i$ communicates with router $j$ by sending a mess...
18.7k
views
answered
Feb 1, 2020
Computer Networks
gateit-2007
computer-networks
routing
binary-tree
normal
+
–
4
votes
9
ISRO2020-74
Following declaration of an array of struct, assumes size of byte, short, int and long are $1,2,3$ and $4$ respectively. Alignment rule stipulates that $n$ - byte field must be located at an address divisible by $n$, the fields in the struct are not rearranged, padding is used ... is located at an address divisble by $8$, what is the total size of $C$, in bytes? $150$ $160$ $200$ $240$
Following declaration of an array of struct, assumes size of byte, short, int and long are $1,2,3$ and $4$ respectively. Alignment rule stipulates that $n$ – byte field...
3.3k
views
answered
Jan 20, 2020
Programming in C
isro-2020
programming
normal
structure
+
–
1
votes
10
what will be the output??
364
views
answered
Jul 29, 2018
0
votes
11
SELF DOUBT PLEASE GIVE EXAMPLE
PLEASE FRAME AN EXAMPLE TO EXPLAIN THE CASES MENTIONED IN THIS The third major event that must be handled by the TCP sender is the arrival of an acknowledgment segment (ACK) from the receiver (more specifically, a segment containing a valid ACK field value) ... control, that data from above is less than MSS in size, and that data transfer is in one direction only. */
PLEASE FRAME AN EXAMPLE TO EXPLAIN THE CASES MENTIONED IN THIS The third major event that must be handled by the TCP sender is the arrival of anacknowledgment segment (...
312
views
answered
Jul 28, 2018
0
votes
12
Process Synchronization
Is there any difference between busy waiting and spinlock What is the meaning of this statement "advantage of a spinlock is that no context switch is required when a process must wait on lock, and a context switch may takes considerable ... expected to be held for short time spinlock are useful" I can't understand this statement Please tell with example..
Is there any difference between busy waiting and spinlockWhat is the meaning of this statement"advantage of a spinlock is that no context switch is required when a proces...
1.3k
views
answered
Jul 28, 2018
2
votes
13
#preemption
If a process comes from block state to ready state then what can be said about preemption ?
If a process comes from block state to ready state then what can be said about preemption ?
346
views
answered
Jul 28, 2018
Operating System
preemption
doubt
+
–
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