Recent activity by dhruvkc123 / GATE Overflow for GATE CSE

3 answers

1

GATE CSE 2004 | Question: 54
$A$ and $B$ are the only two stations on an Ethernet. Each has a steady queue of frames to send. Both $A$ and $B$ attempt to transmit a frame, collide, and $A$ wins the first backoff race. At the end of this successful transmission by $A$, both $A$ ... attempt to transmit and collide. The probability that $A$ wins the second backoff race is: $0.5$ $0.625$ $0.75$ $1.0$

$A$ and $B$ are the only two stations on an Ethernet. Each has a steady queue of frames to send. Both $A$ and $B$ attempt to transmit a frame, collide, and $A$ wins the f...

16.9k views

commented Nov 23, 2019

4 answers

2

GATE CSE 2014 Set 3 | Question: 34
Consider the basic block given below. a = b + c c = a + d d = b + c e = d - b a = e + b The minimum number of nodes and edges present in the DAG representation of the above basic block respectively are $6$ and $6$ $8$ and $10$ $9$ and $12$ $4$ and $4$

Consider the basic block given below. a = b + c c = a + d d = b + c e = d - b a = e + b The minimum number of nodes and edges present in the DAG representation of the abo...

35.2k views

commented Oct 29, 2019

3 answers

3

GATE CSE 1999 | Question: 17
Consider the following program fragment in the assembly language of a certain hypothetical processor. The processor has three general purpose registers $R1, R2$and $R3$. The meanings of the instructions are shown by comments (starting with ;) after the instructions. ... the values n, 0, and 0 respectively. What is the final value of $R3$ when control reaches $Z$?

Consider the following program fragment in the assembly language of a certain hypothetical processor. The processor has three general purpose registers $R1, R2$and $R3$. ...

6.0k views

commented Oct 9, 2017

6 answers

4

GATE CSE 2008 | Question: 73
Consider a machine with a $2$-way set associative data cache of size $64$ Kbytes and block size $16$ bytes. The cache is managed using $32$ bit virtual addresses and the page size is $4$ Kbytes. A program to be run on this machine begins as follows: double ARR[ ... to array $\text{ARR}$. The cache hit ratio for this initialization loop is: $0\%$ $25\%$ $50\%$ $75\%$

Consider a machine with a $2$-way set associative data cache of size $64$ Kbytes and block size $16$ bytes. The cache is managed using $32$ bit virtual addresses and the ...

8.5k views

commented Oct 8, 2017

5 answers

5

ISI2012-PCB-CS-2a
A machine $\mathcal{M}$ has the following five pipeline stages; their respective time requirements in nanoseconds (ns) are given within parentheses: $F$-stage - instruction fetch ($9$ ns), $D$-stage - instruction decode and register fetch ($3$ ns), $X$-stage ... $3$rd instruction needs a $1$ - cycle stall before the $X$-stage. Calculate the CPU time in seconds for completing $P$.

A machine $\mathcal{M}$ has the following five pipeline stages; their respective time requirements in nanoseconds (ns) are given within parentheses:$F$-stage — instruct...

2.6k views

commented Sep 17, 2017

2 answers

6

GATE CSE 2008 | Question: 36
Which of the following are NOT true in a pipelined processor? Bypassing can handle all RAW hazards Register renaming can eliminate all register carried WAR hazards Control hazard penalties can be eliminated by dynamic branch prediction I and II only I and III only II and III only I, II and III

Which of the following are NOT true in a pipelined processor?Bypassing can handle all RAW hazardsRegister renaming can eliminate all register carried WAR hazardsControl h...

22.1k views

commented Sep 17, 2017

2 answers

7

GATE CSE 2001 | Question: 12
Consider a $5-$stage pipeline - IF (Instruction Fetch), ID (Instruction Decode and register read), EX (Execute), MEM (memory), and WB (Write Back). All (memory or register) reads take place in the second phase of a clock cycle ... Show all data dependencies between the four instructions. Identify the data hazards. Can all hazards be avoided by forwarding in this case.

Consider a $5-$stage pipeline - IF (Instruction Fetch), ID (Instruction Decode and register read), EX (Execute), MEM (memory), and WB (Write Back). All (memory or registe...

18.0k views

commented Sep 17, 2017

2 answers

8

limits doubt
llimit 1 / ( 1 + (sin x / x ) ) // can we directly put sin x / x =1 is this valid because its not in product form ? x ->0

llimit 1 / ( 1 + (sin x / x ) ) // can we directly put sin x / x =1 is this valid because its not in product form ?x ->0

317 views

answered Sep 17, 2017

8 answers

9

GATE CSE 2000 | Question: 12
An instruction pipeline has five stages where each stage take 2 nanoseconds and all instruction use all five stages. Branch instructions are not overlapped. i.e., the instruction after the branch is not fetched till the branch instruction ... 50% of the conditional branch instructions are such that the branch is taken, calculate the average instruction execution time.

An instruction pipeline has five stages where each stage take 2 nanoseconds and all instruction use all five stages. Branch instructions are not overlapped. i.e., the ins...

17.5k views

commented Sep 17, 2017

3 answers

10

GATE CSE 1999 | Question: 13
An instruction pipeline consists of $4$ stages - Fetch $(F)$, Decode field $(D)$, Execute $(E)$ and Result Write $(W)$. The $5$ instructions in a certain instruction sequence need these stages for the different number of clock cycles as shown by the ... $5$ instructions.

An instruction pipeline consists of $4$ stages – Fetch $(F)$, Decode field $(D)$, Execute $(E)$ and Result Write $(W)$. The $5$ instructions in a certain instruction se...

10.5k views

commented Sep 17, 2017

11 answers

11

GATE CSE 2001 | Question: 2.13
Consider the following data path of a simple non-pipelined CPU. The registers $A, B$, $A_{1},A_{2}, \textsf{MDR},$ the $\textsf{bus}$ and the $\textsf{ALU}$ are $8$-$bit$ wide. $\textsf{SP}$ and $\textsf{MAR}$ are $16$-$bit$ registers. The ... $\textsf{CPU}$ clock cycles are required to execute the "push r" instruction? $2$ $3$ $4$ $5$

Consider the following data path of a simple non-pipelined CPU. The registers $A, B$, $A_{1},A_{2}, \textsf{MDR},$ the $\textsf{bus}$ and the $\textsf{ALU}$ are $8$-$bit$...

21.2k views

commented Sep 16, 2017

12 answers

12

GATE CSE 2016 Set 2 | Question: 30
Suppose the functions $F$ and $G$ can be computed in $5$ and $3$ nanoseconds by functional units $U_{F}$ and $U_{G}$, respectively. Given two instances of $U_{F}$ and two instances of $U_{G}$, it is required to implement ... $1 \leq i \leq 10$. Ignoring all other delays, the minimum time required to complete this computation is ____________ nanoseconds.

Suppose the functions $F$ and $G$ can be computed in $5$ and $3$ nanoseconds by functional units $U_{F}$ and $U_{G}$, respectively. Given two instances of $U_{F}$ and two...

22.6k views

commented Sep 16, 2017

6 answers

13

GATE CSE 2014 Set 3 | Question: 44
The memory access time is $1$ nanosecond for a read operation with a hit in cache, $5$ nanoseconds for a read operation with a miss in cache, $2$ nanoseconds for a write operation with a hit in cache and $10$ nanoseconds for a write ... cache hit-ratio is $0.9$. The average memory access time (in nanoseconds) in executing the sequence of instructions is ______.

The memory access time is $1$ nanosecond for a read operation with a hit in cache, $5$ nanoseconds for a read operation with a miss in cache, $2$ nanoseconds for a write ...

24.0k views

commented Sep 15, 2017

3 answers

14

GATE CSE 2008 | Question: 35
For inclusion to hold between two cache levels $L_1$ and $L_2$ in a multi-level cache hierarchy, which of the following are necessary? $L_1$ must be write-through cache $L_2$ must be a write-through cache The associativity of $L_2$ must be greater than that of $L_1$ The ... be at least as large as the $L_1$ cache IV only I and IV only I, II and IV only I, II, III and IV

For inclusion to hold between two cache levels $L_1$ and $L_2$ in a multi-level cache hierarchy, which of the following are necessary?$L_1$ must be write-through cache$L_...

24.5k views

commented Sep 15, 2017

3 answers

15

GATE CSE 1999 | Question: 2.23
A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor? Pointers Arrays Records Recursive procedures with local variable

A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this proces...

15.5k views

commented Sep 14, 2017

1 answer

16

GATE CSE 2002 | Question: 10
In a C program, an array is declared as $\text{float} \ A[2048]$. Each array element is $4 \ \text{Bytes}$ in size, and the starting address of the array is $0x00000000$. This program is run on a computer that has a direct ... ? Justify your answer briefly. Assume that the data cache is initially empty and that no other data or instruction accesses are to be considered.

In a C program, an array is declared as $\text{float} \ A[2048]$. Each array element is $4 \ \text{Bytes}$ in size, and the starting address of the array is $0x00000000$....

6.2k views

commented Sep 14, 2017

5 answers

17

GATE CSE 2001 | Question: 1.7, ISRO2008-18
More than one word are put in one cache block to: exploit the temporal locality of reference in a program exploit the spatial locality of reference in a program reduce the miss penalty none of the above

More than one word are put in one cache block to:exploit the temporal locality of reference in a programexploit the spatial locality of reference in a programreduce the m...

17.0k views

commented Sep 13, 2017

5 answers

18

GATE CSE 1996 | Question: 26
A computer system has a three-level memory hierarchy, with access time and hit ratios as shown below: ... of less than $100 nsec$? What is the average access time achieved using the chosen sizes of level $1$ and level $2$ memories?

A computer system has a three-level memory hierarchy, with access time and hit ratios as shown below:$$\overset{ \text {Level $1$ (Cache memory)} \\ \text{Access time = ...

15.1k views

commented Sep 13, 2017

6 answers

19

GATE CSE 1993 | Question: 11
In the three-level memory hierarchy shown in the following table, $p_i$ denotes the probability that an access request will refer to $M_i$ ... a page swap is $T_i$. Calculate the average time $t_A$ required for a processor to read one word from this memory system.

In the three-level memory hierarchy shown in the following table, $p_i$ denotes the probability that an access request will refer to $M_i$.$$\begin{array}{|c|c|c|c|} \hli...

11.0k views

commented Sep 13, 2017

0 answers

20

addressing modes
Assume that the instruction is stored in the memory which is byte addressable and starting address is is 704 (decimal system ).

Assume that the instruction is stored in the memory which is byte addressable and starting address is is 704 (decimal system ).

592 views

commented Sep 7, 2017

2 answers

21

Forouzan Flow Control
A) A system uses the Stop-and Wait ARQ Protocol. If each packet carries 1000 bits of data. Determine how long does it take to send 1 million bits of data if the distance between the sender and receiver is 5000 Km and the propagation speed is ... exercise A using the selective repeat ARQ Protocol with a window size of 4. Ignore the overhead due to the header and trailer.

A) A system uses the Stop-and Wait ARQ Protocol. If each packet carries 1000 bits of data. Determine how long does it take to send 1 million bits of data if the distance ...

5.5k views

comment edited Sep 4, 2017

4 answers

22

GATE IT 2005 | Question: 74
In a communication network, a packet of length $L$ bits takes link $L_1$ with a probability of $p_1$ or link $L_2$ with a probability of $p_2$. Link $L_1$ and $L_2$ have bit error probability of $b_1$ and $b_2$ respectively. The probability that the packet will be received without ... $[1 - (b_1 + b_2)^L]p_1p_2$ $(1 - b_1)^L (1 - b_2)^Lp_1p_2$ $1 - (b_1^Lp_1 + b_2^Lp_2)$

In a communication network, a packet of length $L$ bits takes link $L_1$ with a probability of $p_1$ or link $L_2$ with a probability of $p_2$. Link $L_1$ and $L_2$ have ...

8.9k views

commented Sep 3, 2017

0 answers

23

data communication and network
host a needs to send a payload size of 2400 bytes to host B across the network having MTU of 400 bytes if fragmentation takes place how many fragment will be there & what will be the data data length of each fragment?

host a needs to send a payload size of 2400 bytes to host B across the network having MTU of 400 bytes if fragmentation takes place how many fragment will be there & wha...

659 views

commented Sep 3, 2017

1 answer

24

Test by Bikram | Computer Networks | Test 1 | Question: 5
A class C network is sub divided into subnets with $3$ bit subnet number, the maximum number of available hosts in each sub network is __________

A class C network is sub divided into subnets with $3$ bit subnet number, the maximum number of available hosts in each sub network is __________

493 views

commented Sep 3, 2017

1 answer

25

Test by Bikram | Computer Networks | Test 1 | Question: 23
The bandwidth in a Stop n Wait ARQ is $1$ Gbps and $1$ bit delay to make round trip time $30$ microseconds, if data frames are $2000$ bits in length then the link is utilized in __________ percentage.

The bandwidth in a Stop n Wait ARQ is $1$ Gbps and $1$ bit delay to make round trip time $30$ microseconds, if data frames are $2000$ bits in length then the link is util...

1.0k views

commented Sep 3, 2017

3 answers

26

Test by Bikram | Computer Networks | Test 1 | Question: 25
A $3000$ km long trunk operates at $1.536\times 10^6$ bps and is used to transmit $64$ byte frames using sliding window protocol. If the propagation speed is $6$ microseconds/km then the number of bits needed for the sequence number for maximum efficiency is _______

A $3000$ km long trunk operates at $1.536\times 10^6$ bps and is used to transmit $64$ byte frames using sliding window protocol. If the propagation speed is $6$ microsec...

1.4k views

comment reshown Sep 3, 2017

3 answers

27

Test by Bikram | Computer Networks | Test 1 | Question: 21
Let the number of bits used to represent the frame sequence number is $x$ then the total number of frames in the sliding window can be send from sender side using Go Back $N$ is : $1$ $2x$ $2x - 1$ $2(x - 1)$

Let the number of bits used to represent the frame sequence number is $x$ then the total number of frames in the sliding window can be send from sender side using Go Back...

474 views

commented Sep 3, 2017

2 answers

28

Test by Bikram | Computer Networks | Test 1 | Question: 16
In a token bucket network transmission spreed is $20^*(10^6)$ bps and maximum rate can only be sent for at most $10$ sec at a time, and at most $150$ Mb can be sent over any $15$ sec window, then the value for token input rate is _________ mbps

In a token bucket network transmission spreed is $20^*(10^6)$ bps and maximum rate can only be sent for at most $10$ sec at a time, and at most $150$ Mb can be sent over...

1.2k views

commented Sep 3, 2017

1 answer

29

Test by Bikram | Computer Networks | Test 1 | Question: 7
Consider private key crypto-system has $3$ keys, $3$ plain-texts and $4$ cipher-texts: $K=\{ k1,k2,k3 \}$ $M=\{m1, m2,m3 \}$ $C=\{c1,c2,c3,c4 \}$ In a valid encryption table find the key that maps two different messages to same cipher text: k1 k2 k3 No key can map

Consider private key crypto-system has $3$ keys, $3$ plain-texts and $4$ cipher-texts:$K=\{ k1,k2,k3 \}$$M=\{m1, m2,m3 \}$$C=\{c1,c2,c3,c4 \}$In a valid encryption table ...

494 views

commented Sep 3, 2017

1 answer

30

Test by Bikram | Computer Networks | Test 1 | Question: 4
Routers can be configured using several sources, which among these can not be used for Router Configuration? Removable media Console port TFTP server Virtual terminals

Routers can be configured using several sources, which among these can not be used for Router Configuration?Removable mediaConsole portTFTP serverVirtual terminals

685 views

commented Sep 3, 2017

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