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Questions by goxul

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In a normal 5-stage pipeline, when is the branch target address available? There are some sources which say that the address is available after the MEM stage, but go on to say that it can be found out after the ID stage if we put in an extra adder. ... question in which they assumed that the address is available after the 4th stage. Is that the approach to be followed for all the questions?
asked Dec 11, 2018 in CO and Architecture 216 views
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Here, in the DADDI instruction, there are only two stalls. But since there is no operand forwarding, won't the contents of the register be available after they've been written into the register file and so, there should be three stalls? From what I could understand in this question, the value of the registers is available after the M stage, before it is written.
asked Aug 17, 2018 in CO and Architecture 82 views