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Questions by gshivam63
1
votes
0
answers
1
GATE 2016-2-30
Can anyone draw the pipeline diagram for this question? https://gateoverflow.in/39627/gate-2016-2-30
Can anyone draw the pipeline diagram for this question?https://gateoverflow.in/39627/gate-2016-2-30
501
views
asked
Jul 31, 2016
1
votes
1
answer
2
DFS
Consider the following graph G modified DFS on G is as folows: starting vertex is 'a' vertex is visited on alphabetic order vertices are visited in order a,c,d,..... it works same as DFS except the visiting order restriction Which of the following is not a back edge during above DFA traversal on G? (a) {f,b} (b) {e,a} (c){d,a} (d){c,a}
Consider the following graph G modified DFS on G is as folows:starting vertex is 'a'vertex is visited on alphabetic ordervertices are visited in order a,c,d,.....it works...
1.8k
views
asked
Jul 25, 2016
Algorithms
algorithms
graph-algorithms
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–
3
votes
2
answers
3
BFS
Consider two vertices a and b that are simultaneously on the FIFO queue at same point during the execution of breadth first search from s in an undirected graph. Which of the following is true? 1. The number of edges on the shortest path between s and a is atmost one more than the number of edges on ... and b. 3. There is a path between a and b. a.1 only b.1 and 2 only c. 2 only d. 1, 2 and 3
Consider two vertices a and b that are simultaneously on the FIFO queue at same point during the execution of breadth first search from s in an undirected graph.Which of ...
18.1k
views
asked
Jul 25, 2016
Algorithms
algorithms
breadth-first-search
shortest-path
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–
1
votes
1
answer
4
Madeeasy workbook
A researcher wishes to digitally record analog sounds for testing animal hearing with frequencies of upto 100 kHz. Use Shannon's formula to find minimum signal to noise ratio (in dB) required to sustain the given data rate over a 500 KHz radio channel. a. 19.2 b. 18 c. 14 d. 19.5
A researcher wishes to digitally record analog sounds for testing animal hearing with frequencies of upto 100 kHz. Use Shannon's formula to find minimum signal to noise r...
1.4k
views
asked
Jul 12, 2016
5
votes
4
answers
5
Tanenbaum NAK and Retransmission
Compute the fraction of the bandwidth that is wasted on overheads(headers and retransmission ) for protocol 6 on a heavily loaded 50 kbps satellite channel with data frames consisting of 40 headers and 3960 data bits.Assume that the signal propagation time ... for data frames is 1%, and the error rate for NAK frames is negligible.The sequence numbers are 8 bits.
Compute the fraction of the bandwidth that is wasted on overheads(headers and retransmission ) for protocol 6 on a heavily loaded 50 kbps satellite channel with data fram...
3.2k
views
asked
Jul 12, 2016
Computer Networks
tanenbaum
computer-networks
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–
9
votes
2
answers
6
Madeeasy workbook
An upper layer packet is split into 10 frames, each of which has an 80% chance of arriving undamaged. If no error is done by the data link protocol, how many times must the message be sent on average to get the entire thing through?
An upper layer packet is split into 10 frames, each of which has an 80% chance of arriving undamaged. If no error is done by the data link protocol, how many times must t...
7.5k
views
asked
Jul 12, 2016
8
votes
1
answer
7
GATE CSE 1990 | Question: 4-iv
Transferring data in blocks from the main memory to the cache memory enables an interleaved main memory unit to operate unit at its maximum speed.True/False.Explain.
Transferring data in blocks from the main memory to the cache memory enables an interleaved main memory unit to operate unit at its maximum speed.True/False.Explain.
4.3k
views
asked
Jul 2, 2016
CO and Architecture
gate-1990
true-false
co-and-architecture
cache-memory
memory-interleaving
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–
0
votes
1
answer
8
Gate
Whether Vectored Interrupts are possible on CPU having single Interrupt Request line and a single interrupt grant line?
Whether Vectored Interrupts are possible on CPU having single Interrupt Request line and a single interrupt grant line?
401
views
asked
Jul 2, 2016
1
votes
0
answers
9
Madeeasy Cache Organization
Consider the direct mapped cache organization consists of m-lines with a line size of 2w words/bytes. Main memory address can be viewed as consisting of three fields.The least significant w-bits identify a unique word within the block of main memory.The remaining 'S' bits specify one of the 2^S block ... -m+1,.......,2S-1 (c)1,2,3,......,m-1 (d)0,2,4,......,m-1
Consider the direct mapped cache organization consists of m-lines with a line size of 2w words/bytes. Main memory address can be viewed as consisting of three fields.The ...
768
views
asked
Jun 30, 2016
3
votes
2
answers
10
Madeeasy
Assume that interrupt processing takes 75us. Interrupt driven I/O for a device that transfer data an average of 8KB/sec on a continuous basis.Find percentage of the processor time is consumed by the I/O device if it interrupts for every byte? a. 20 b. 40 c.60 d.80
Assume that interrupt processing takes 75us. Interrupt driven I/O for a device that transfer data an average of 8KB/sec on a continuous basis.Find percentage of the proce...
2.7k
views
asked
Jun 29, 2016
2
votes
2
answers
11
Madeeasy
DMA is transferring characters to the processor, from a device transmitting at 16000 bits per second. Assume DMA is using cycle stealing, If the Processor needs access to main memory once every microsecond, find how much percentage will the processor be slowed down due to DMA activity? a. 0.20 b 0.25 c.0.30 d.0.35
DMA is transferring characters to the processor, from a device transmitting at 16000 bits per second. Assume DMA is using cycle stealing, If the Processor needs access to...
2.6k
views
asked
Jun 29, 2016
6
votes
1
answer
12
Madeeasy
Suppose DMA is employed in two modes 1)Cycle Steaking Mode 2)Burst Mode Transfer of bus control from CPU to I/O or I/O to CPU takes 300ns. Assume the system in which bus cycle takes 700ns and one of the I/O device has a data transfer rate of 50KB/sec and employs DMA ... 1) & (2) (1)Cycle Stealing Mode Options a.100us b.110us c.120us d.130us (2)Burst Mode Options a.1msec b.2msec c.3msec
Suppose DMA is employed in two modes1)Cycle Steaking Mode2)Burst ModeTransfer of bus control from CPU to I/O or I/O to CPU takes 300ns. Assume the system in which bus cyc...
3.6k
views
asked
Jun 29, 2016
CO and Architecture
co-and-architecture
dma
io-organization
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–
0
votes
1
answer
13
Madeeasy
Which of the following storage allocation is faster in general? a)Best FIt b)First Fit c)Worst Fit d)All of these
Which of the following storage allocation is faster in general?a)Best FItb)First Fitc)Worst Fitd)All of these
3.6k
views
asked
Jun 29, 2016
0
votes
1
answer
14
Calculate the speed up.
An assembly language applicationcontains 1200 assembly language instructions.It takes 12 second to run on benchmark.The application programmer then works on the assembly language code to make it better after this the application takes 10 seconds to run.Calculate the speed up. (a)12 (b)5/6 (c)1.2 (d)1.0
An assembly language applicationcontains 1200 assembly language instructions.It takes 12 second to run on benchmark.The application programmer then works on the assembly ...
848
views
asked
Jun 29, 2016
1
votes
1
answer
15
DRDO 2009
The address bus of a computer has 16 address lines,A15_0 If the address assigned to one deviceis 7CA416 and the address decoder for that deviceignores lines A8 and A9, what are all theaddresses to which this device will respond? (a)7CA416,7CA516,7CA616,7CA716 (b)7C8416,7C9416,7CA416,7CB416 (c)7CA416,7DA416,7EA416,7FA416 (d)7CA416,6CA416,5CA416,4CA416
The address bus of a computer has 16 address lines,A15_0 If the address assigned to one deviceis 7CA416 and the address decoder for that deviceignores lines A8 and A9, wh...
2.4k
views
asked
Jun 29, 2016
0
votes
0
answers
16
Can you explain how lockup free cache design allow cpu to work even when a miss is encountered?
231
views
asked
Jun 28, 2016
1
votes
1
answer
17
Choose the correct option?
Consider a computer system that has a cache with 512 blocks each of which can store 32 bytes.All addresses are byte addresses.Which Cache set will the memory address 0xFBFC map to if the cache is direct mapped (a)1DC (b)1CF (c)DF1 (d)DAC
Consider a computer system that has a cache with 512 blocks each of which can store 32 bytes.All addresses are byte addresses.Which Cache set will the memory address 0xFB...
1.4k
views
asked
Jun 28, 2016
3
votes
1
answer
18
what is hit ratio?
In a 2 level memory, if the level 1 memory is 5 times faster than level 2 and its access time is 10ns less than avg access time.Let the level 1 memory access time is 20ns. (a.)0.7 (b.)0.75 (c.)0.86 (d.)0.96
In a 2 level memory, if the level 1 memory is 5 times faster than level 2 and its access time is 10ns less than avg access time.Let the level 1 memory access time is 20ns...
3.3k
views
asked
Jun 28, 2016
1
votes
1
answer
19
Identify the correct option?
For which register, the effective register (BX) EA=(DI) is (SI) a) relative base indexed b)register indirect c)base indexed d)register relative
For which register, the effective register (BX) EA=(DI) is (SI) a) relativ...
978
views
asked
Jun 14, 2016
0
votes
0
answers
20
what is the tight bound for this expression?
1^k+2^k+3^k+..........n^k =n^k+n^k+n^k+........n^k(n times) =n^(k+1)=O(nk+1) But this is the actual tight bound or it can further be minimized?
1^k+2^k+3^k+..........n^k=n^k+n^k+n^k+........n^k(n times)=n^(k+1)=O(nk+1)But this is the actual tight bound or it can further be minimized?
309
views
asked
Jun 3, 2016
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