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Answers by habedo007
1
vote
1
T(n) = T(n/2) + n recurrence equation solution? T(1) = 1.
suppose you are given n bit integers asuming for common sense n as power of 2 .it is required to multiply them using divide and conquer method .what is the divide and conquer recurrence that would arise for the problem a) T(n)=4T(n/2)+c b) a) T(n)=2T(n/2)+n c) a) T(n)=4T(n/2)+n2 d) a) T(n)=4T(n)+n
answered
in
Algorithms
Nov 20, 2020
4.9k
views
algorithms
recurrence-relation
1
vote
2
NIELIT 2017 DEC Scientific Assistant A - Section B: 37
How many times the word "PROCESS" will be printed when executing the following program ? main(){ printf("PROCESS"); fflush(); fork(); fork(); } $8$ $4$ $6$ $7$
answered
in
Operating System
Oct 13, 2020
738
views
nielit2017dec-assistanta
operating-system
system-call
1
vote
3
NIELIT 2017 July Scientist B (CS) - Section B: 47
What is the maximum number of reduce moves that can be taken by a bottom-up parser for a grammar with no epsilon and unit production (i.e.,of type $A\to\epsilon$ and $A \to a)$ to parse a string with $n$ tokens? $n/2$ $n-1$ $2n-1$ $2^n$
answered
in
Compiler Design
Oct 9, 2020
623
views
nielit2017july-scientistb-cs
compiler-design
grammar
0
votes
4
NIELIT 2017 July Scientist B (CS) - Section B: 57
A system program that combines the separately complied modules of a program into a form suitable for execution assembler linking loader cross compiler load and go
answered
in
Compiler Design
Oct 6, 2020
509
views
nielit2017july-scientistb-cs
compiler-design
linker
1
vote
5
NIELIT 2017 DEC Scientist B - Section B: 28
A RAM chip has $7$ address lines, $8$ data lines and $2$ chips select lines. Then the number of memory locations is __________ $2^{12}$ $2^{10}$ $2^{19}$ $2^{13}$
answered
in
CO and Architecture
Oct 4, 2020
1.3k
views
nielit2017dec-scientistb
co-and-architecture
memory-interfacing
0
votes
6
time complexity
The running time of an algorithm T(n), where ‘n’ is the input size, is given by— T(n)=8⌈(n/2)+qn,if n>1⌉=p,if n=1 where p, q are constants. The order of this algorithm is— (a) n2 (b) nn (c) n3 (d) n
answered
in
Algorithms
Apr 8, 2020
9.9k
views
time-complexity
recurrence-relation
0
votes
7
ISRO2014-17
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a $4 \times 6$ array, where each chip is $8\;\text{K} \times 4$ bits? $13$ $15$ $16$ $17$
answered
in
CO and Architecture
Mar 30, 2020
8.6k
views
co-and-architecture
memory-interfacing
isro2014
1
vote
8
Recognize the language
If L be a language recognizable by a finite automata, then language from {L}={w such that w is prefix of v where v belongs to L},is a a. Regular Language b. Context Free language c. Context Sensitive Language d. Recursive Enumerable Language
answered
in
Theory of Computation
Mar 28, 2020
2.7k
views
3
votes
9
NIELIT 2018-49
The following table has two attributes $X$ and $Y$ where $X$ is the primary key and $Y$ is the foreign key referencing $X$ ... $(4,3)$ and $(6,4)$ $(2,4)$ and $(7,2)$ $(3,2)$ and $(9,5)$ $(3,4), (4,5)$ and $(6,4)$
answered
in
Databases
Mar 24, 2020
2.6k
views
nielit-2018
databases
referential-integrity
3
votes
10
BCD adder to add 2 decimal digits needs
The BCD adder to add two decimal digits needs minimum of 6 full adders, 2 half adders 5 full adders, 3 half adders 4 full adders, 3 half adders 5 full adders, 2 half adders
answered
in
Digital Logic
Mar 24, 2020
13.8k
views
adder
0
votes
11
ISRO2020-50
If every non-key attribute functionally dependent on the primary key, then the relation will be in First normal form Second normal form Third normal form Fourth Normal form
answered
in
Databases
Jan 13, 2020
6.4k
views
isro-2020
databases
database-normalization
easy
0
votes
12
ISRO2020-32
$G$ is an undirected graph with vertex set $\{v1, \ v2, \ v3, \ v4, \ v5, \ v6, \ v7\}$ and edge set $\{v1v2,\ v1v3,\ v1v4\ ,v2v4,\ v2v5,\ v3v4,\ v4v5,\ v4v6,\ v5v6,\ v6v7\ \}$. A breadth first search of the graph is performed with $v1$ as the root node. Which of the following is a tree edge? $v2v4$ $v1v4$ $v4v5$ $v3v4$
answered
in
DS
Jan 13, 2020
2.3k
views
isro-2020
data-structures
breadth-first-search
normal
1
vote
13
ISRO2020-34
Huffman tree is constructed for the following data :$\{A,B,C,D,E\}$ with frequency $\{0.17,0.11,0.24,0.33\ \text{and} \ 0.15 \}$ respectively. $100\ 00\ 01101$ is decoded as $BACE$ $CADE$ $BAD$ $CADD$
answered
in
Algorithms
Jan 13, 2020
2.7k
views
isro-2020
algorithms
huffman-code
normal
2
votes
14
ISRO2020-12
If $ABCD$ is a $4$-bit binary number, then what is the code generated by the following circuit? BCD code Gray code $8421$ code Excess-$3$ code
answered
in
Digital Logic
Jan 13, 2020
1.8k
views
isro-2020
digital-logic
combinational-circuit
circuit-output
normal
3
votes
15
ISRO2020-72
A stack is implemented with an array of $'A[0...N-1]'$ and a variable $pos$'. The push and pop operations are defined by the following code. push (x) A[pos] <- x pos <- pos -1 end push pop() pos <- pos+1 return A[pos] end pop ... an empty stack with capacity $N$ for the above implementation $pos \leftarrow -1$ $pos\leftarrow 0$ $pos\leftarrow 1$ $pos\leftarrow N-1$
answered
in
DS
Jan 13, 2020
2.1k
views
isro-2020
data-structures
stack
normal
1
vote
16
ISRO2020-77
Consider the following circuit The function by the network above is $\overline{AB}E+EF+\overline{CD}F$ $(\overline{E}+AB\overline{F})(C+D+\overline{F})$ $(\overline{AB}+E)(\overline{E}+\overline{F})(C+D+\overline{F})$ $(A+B)\overline{E} +\overline{EF}+CD\overline{F}$
answered
in
Digital Logic
Jan 13, 2020
1.6k
views
isro-2020
digital-logic
combinational-circuit
circuit-output
normal
4
votes
17
ISRO2020-76
If $A=\{x,y,z\}$ and $B=\{u,v,w,x\}, $ and the universe is $\{s,t,u,v,w,x,y,z\}$. Then $(A \cup \overline{B}) \cap (A \cap B)$ is equal to $\{u,v,w,x\}$ $\{ \: \}$ $\{u,v,w,x,y,z\}$ $\{u,v,w\}$
answered
in
Set Theory & Algebra
Jan 13, 2020
860
views
isro-2020
discrete-mathematics
set-theory&algebra
set-theory
easy
1
vote
18
ISRO2020-26
The operating system and the other processes are protected from being modified by an already running process because they run at different time instants and not in parallel they are in different logical addresses they use a protection algorithm in the scheduler every address generated by the CPU is being checked against the relocation and limit parameters
answered
in
Operating System
Jan 13, 2020
2.8k
views
isro-2020
operating-system
process-synchronization
easy
3
votes
19
ISRO2020-67
What is the availability of the software with the following reliability figures Mean Time Between Failures (MTBF) is $20$ days Mean Time To Repair (MTTR) is $20$ hours $90\%$ $96\%$ $24\%$ $50\%$
answered
in
IS&Software Engineering
Jan 13, 2020
2.8k
views
isro-2020
is&software-engineering
normal
1
vote
20
GATE CSE 2019 | Question: 35
Consider the first order predicate formula $\varphi$: $\forall x [ ( \forall z \: z | x \Rightarrow (( z=x) \vee (z=1))) \rightarrow \exists w ( w > x) \wedge (\forall z \: z | w \Rightarrow ((w=z) \vee (z=1)))]$ Here $a \mid b$ denotes ... of all integers Which of the above sets satisfy $\varphi$? $S_1$ and $S_2$ $S_1$ and $S_3$ $S_2$ and $S_3$ $S_1, S_2$ and $S_3$
answered
in
Mathematical Logic
Nov 12, 2019
15.4k
views
gatecse-2019
engineering-mathematics
discrete-mathematics
mathematical-logic
first-order-logic
2-marks
3
votes
21
GATE CSE 2014 Set 1 | Question: 28
Consider a selective repeat sliding window protocol that uses a frame size of $1$ $\text{KB}$ to send data on a $1.5$ $\text{Mbps}$ link with a one-way latency of $50$ $\text{msec}$. To achieve a link utilization of $60\%$, the minimum number of bits required to represent the sequence number field is ________.
answered
in
Computer Networks
Nov 6, 2018
22.1k
views
gatecse-2014-set1
computer-networks
sliding-window
numerical-answers
normal
1
vote
22
NIELIT2017 STA-set-c-119
The function $f(x)=\frac{x^2 -1}{x-1}$ at $x=1$ is: Continuous and Differentiable Continuous but not Differentiable Differentiable but not Continuous Neither Continuous nor Differentiable
answered
in
Calculus
Oct 28, 2018
964
views
nielit-july-2017
engineering-mathematics
calculus
continuity
1
vote
23
ISRO-DEC2017-36
Station $A$ uses $32-byte$ packets to transmit messages to Station $B$ using a sliding window protocol. The round trip time delay between $A$ and $B$ is $40\,ms$ and the bottleneck bandwidth on the path $A$ and $B$ is $64\, kbps.$What is the optimal window size that $A$ should use? $5$ $10$ $40$ $80$
answered
in
Computer Networks
Apr 21, 2018
1.3k
views
isrodec2017
11
votes
24
GATE CSE 2018 | Question: 34
The size of the physical address space of a processor is $2^P$ bytes. The word length is $2^W$ bytes. The capacity of cache memory is $2^N$ bytes. The size of each cache block is $2^M$ words. For a $K$-way set-associative cache memory, the length (in number of bits) of the tag field is $P-N- \log_2K$ $P-N+ \log_2 K$ $P-N-M-W- \log_2 K$ $P-N-M-W+ \log_2 K$
answered
in
CO and Architecture
Feb 24, 2018
8.7k
views
gatecse-2018
co-and-architecture
cache-memory
normal
2-marks
5
votes
25
ISRO-DEC2017-47
Which of the following permutation can be obtained in the same order using a stack assuming that input is the sequence $5,6,7,8,9$ in that order? $7,8,9,5,6$ $5,9,6,7,8$ $7,8,9,6,5$ $9,8,7,5,6$
answered
in
DS
Feb 11, 2018
1.5k
views
isrodec2017
3
votes
26
ISRO-DEC2017-25
Let $L=\{a^p\mid p \text{ is a prime}\}.$ Then which of the following is true It is not accepted by a Turing Machine It is regular but not context-free It is context-free but not regular It is neither regular nor context-free ,but accepted by a Turing Machine
answered
in
Theory of Computation
Feb 8, 2018
898
views
isrodec2017
14
votes
27
ISRO-DEC2017-17
If $C$ is a skew-symmetric matrix of order $n$ and $X$ is $n\times 1$ column matrix, then $X{^T} CX$ is a scalar matrix null matrix unit matrix matrix will all elements $1$
answered
in
Linear Algebra
Feb 8, 2018
2.3k
views
isrodec2017
matrix
1
vote
28
ISRO-DEC2017-6
The proposition $(P\Rightarrow Q)\wedge (Q\Rightarrow P)$ is a Tautology Contradiction Contingency Absurdity
answered
in
Mathematical Logic
Feb 1, 2018
1.7k
views
isrodec2017
19
votes
29
GATE CSE 2014 Set 2 | Question: 55
Consider the main memory system that consists of $8$ memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for $100$ nanoseconds (ns) by the data, address, and control signals. ... bus at any time. The maximum number of stores (of one word each) that can be initiated in $1$ millisecond is ________
answered
in
Operating System
Dec 22, 2017
17.6k
views
gatecse-2014-set2
operating-system
memory-management
numerical-answers
normal
7
votes
30
GATE CSE 2010 | Question: 31
What is the boolean expression for the output $f$ of the combinational logic circuit of NOR gates given below? $\overline{Q+R}$ $\overline{P+Q}$ $\overline{P+R}$ $\overline{P+Q+R}$
answered
in
Digital Logic
Nov 18, 2017
9.3k
views
gatecse-2010
digital-logic
circuit-output
normal
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