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Questions by habedo007

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1

CGPDTM-2015-2
To successfully prevent user programs from causing damage to other programs or OS, hardware support is required. Name the hardware mechanisms in modern CPUs that support this goal and describe what specific kinds of damage it prevents.

asked in Operating System Oct 28, 2018

231 views

0 votes

1 answer

2

NIELIT2017 STA-set-c-119
The function $f(x)=\frac{x^2 -1}{x-1}$ at $x=1$ is: Continuous and Differentiable Continuous but not Differentiable Differentiable but not Continuous Neither Continuous nor Differentiable

asked in Calculus Aug 31, 2018

955 views

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1 answer

3

DMA CPU consumed or blocked
In DMA, there are two modes of transferring data: burst and cycle stealing. Also, there are two states of CPU when operating DMA: either it's blocked or consumed. I want to know whether CPU is blocked or consumed when operating in burst mode, and same for cycle stealing mode.

asked in CO and Architecture Jul 5, 2018

523 views

0 votes

1 answer

4

Cache Coherence
A system with 2 cores $C0$ and $C1$ uses Write–invalidate Snoopy cache coherency protocol with $Valid$, $Dirty$ and $Shared$ bits. A program runs on the system where $C0$ writes to $A$ and afterwards $C1$ reads from $A$. This happens for 1000 times. Find number of times system bus is used by the program..

asked in CO and Architecture May 8, 2018

613 views

0 votes

1 answer

5

Consider the following graph L and find the bridges, if any
A) No bridge B) {d, e} C) {c, d} D) {c, d} and {c, f}

asked in DS Aug 18, 2017

1.8k views

3 votes

0 answers

6

Effective memory access time
What has to be the general and final formula for calculating the effective memory access time, taking in consideration the $\alpha$-level page table, TLB hit ratio as $h$, miss ratio as $m$, memory access time as $M$ ... for page fault servicing as $x$? There seems to be so many formulae, each different from each other depending on the question.

asked in CO and Architecture Aug 18, 2017

812 views

4 votes

1 answer

7

Multilevel TLB performance
A computer has a 128-entry $L_1$ TLB, 1024-entry $L_2$ TLB, and uses page size of 4KB. A program reads a 1MB array, one byte at a time from start to end, 10 times. Assuming the TLBs are directly mapped and initially empty, and no other memory is accessed, find TLB hits and misses of both $L_1$ and $L_2$ TLB (array is page aligned).

asked in Operating System Aug 8, 2017

748 views

1 vote

1 answer

8

Different equations for Bandwidth delay product from different writers
"Computer Networks" By A. Tannenbaum says that Bandwidth delay product is determined by the bandwidth in bits/sec multiplied by the one-way transit time, and then multiplied the bandwidth of 50kbps with half of ... finding that the Formula for Bandwidth delay product is $Bandwidth \times RTT$RTT. Which one is correct?

asked in Computer Networks Jul 12, 2017

539 views

5 votes

4 answers

9

ISRO2016-48
Determine the number of page faults when references to pages occur in the following order: 1, 2, 4, 5, 2, 1, 2, 4 Assume that the main memory can accommodate 3 pages and the main memory already has the pages 1 and 2, with page one having brought earlier than page 2. (LRU page replacement algorithm is used) 3 5 4 None of these

asked in Operating System Jul 5, 2016

7.2k views

5 votes

3 answers

10

ISRO2016-41
A top-down parser generates Rightmost Derivation Rightmost derivation in reverse Leftmost derivation Leftmost derivation in reverse

asked in Compiler Design Jul 5, 2016

11.3k views