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MadeEasy Subject Test 2019: Theory of Computation - Closure Property
Consider the following Statements : There Exist a non-deterministic CFL whose reversal is DCFL. There exist a non regular CSL whose Kleene Closure is regular. Which of following are True ? Explain with reasons.
Consider the following Statements :There Exist a non-deterministic CFL whose reversal is DCFL.There exist a non regular CSL whose Kleene Closure is regular.Which of follo...
1.0k
views
answered
Jan 24, 2019
Theory of Computation
theory-of-computation
closure-property
made-easy-test-series
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0
answers
2
MadeEasy Test Series: Digital Logic - Logic Gates
A bulb in a stair case has two switches, one switch being at the ground floor and other at the first floor. The bulb can be turned ON and also can be turned OFF by any one of the switches irrespective of the state of the other switch. What ... of the state of the other switch so I think, it should be OR gate. What should be the answer? OR or XOR
A bulb in a stair case has two switches, one switch being at the ground floor and other at the first floor. The bulb can be turned ON and also can be turned OFF by any on...
477
views
asked
Jan 8, 2019
Digital Logic
made-easy-test-series
digital-logic
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1
answer
3
Computer network tcp congestion control
730
views
commented
Jan 7, 2019
Computer Networks
congestion-control
tcp
computer-networks
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0
answers
4
me test
Consider an instance of TCP's Additive Increase Multiplicative Decrease (AIMD) algorithm where the window size at the start of slow start phase is 2 MSS and the threshold at the start of 1 st transmission is 16 MSS. Assume TCP use over a lossy link i.e., timeout ... window at the start of slow start phase is 2 MSS ;so when timeout occur should'nt we start with window size of 2 MSS]
Consider an instance of TCP's Additive Increase Multiplicative Decrease (AIMD) algorithm where the window size at the start of slow start phase is 2 MSS and the threshold...
480
views
commented
Jan 7, 2019
Computer Networks
computer
computer-networks
congestion-control
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3
answers
5
Gateoverflow Computer architecture 2 exam question
Suppose there are 500 memory references in which 50 misses in the 1st level cache and 20 misses in the 2nd level cache . Let the miss penalty from L2 cache to memory is 100 cycles . Hit time in L2 cache is 20 cycles and hit ... per instruction will be __________ Ans is : 15 Can any explain how to solve this type of question, Thanks in advance.
Suppose there are 500 memory references in which 50 misses in the 1st level cache and 20 misses in the 2nd level cache . Let the miss penalty from L2 cache to memory is 1...
1.3k
views
commented
Dec 30, 2018
CO and Architecture
co-and-architecture
cache-memory
stall-cycle-per-instrution
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