Recent activity by hsd31196 / GATE Overflow for GATE CSE

1 answer

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I want to be an ML researcher but don't have any guidance and don't have money for coaching?

822 views

commented Jul 5, 2018

0 answers

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Admission
How is MANIT bhopal for Mtech CSE?

How is MANIT bhopal for Mtech CSE?

197 views

asked Mar 31, 2018

0 answers

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Gate 2018
Gate score :560 Category :Gen Which college should I apply? Heard this year PSUs are given chance to recruit first and IITs are going to fill vacant seats by conducting extra rounds.

Gate score :560Category :GenWhich college should I apply?Heard this year PSUs are given chance to recruit first and IITs are going to fill vacant seats by conducting extr...

282 views

asked Mar 17, 2018

3 answers

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GATE CSE 2018 | Question: 36
Consider the following problems. $L(G)$ denotes the language generated by a grammar $G$. L(M) denotes the language accepted by a machine $M$. For an unrestricted grammar $G$ and a string $w$, whether $w \in L(G)$ Given a Turing machine ... is correct? Only I and II are undecidable Only II is undecidable Only II and IV are undecidable Only I, II and III are undecidable

Consider the following problems. $L(G)$ denotes the language generated by a grammar $G$. L(M) denotes the language accepted by a machine $M$.For an unrestricted grammar $...

16.8k views

commented Feb 14, 2018

7 answers

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GATE CSE 2018 | Question: 37
A lexical analyzer uses the following patterns to recognize three tokens $T_1, T_2$, and $T_3$ over the alphabet $\{a, b, c\}$. $T_1: a?(b \mid c)^\ast a$ $T_2: b?(a \mid c)^\ast b$ ... the string $bbaacabc$ is processed by the analyzer, which one of the following is the sequence of tokens it outputs? $T_1T_2T_3$ $T_1T_1T_3$ $T_2T_1T_3$ $T_3T_3$

A lexical analyzer uses the following patterns to recognize three tokens $T_1, T_2$, and $T_3$ over the alphabet $\{a, b, c\}$.$T_1: a?(b \mid c)^\ast a$$T_2: b?(a \mid c...

21.3k views

commented Feb 14, 2018

2 answers

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Gate 2018
NFA to DFA..no of states answer

NFA to DFA..no of states answer

1.3k views

commented Feb 5, 2018

1 answer

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Gate Made Easy Mock Test
A system uses optimal policy for a page replacement. It has 4 page frames with no pages loaded to begin with. Consider the following scenario Case-1: System first accesses 200 distinct pages in sequential order and then access same 200 distinct ... access same 200 distinct page in reverse order. The difference in the number of faults occurred in both case are _________.

A system uses optimal policy for a page replacement. It has 4 page frames with no pages loaded to begin with. Consider the following scenarioCase-1: System first accesses...

1.3k views

commented Jan 15, 2018

5 answers

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GATE IT 2007 | Question: 66
Consider the following two transactions$: T1$ and $T2.$ ...

Consider the following two transactions$: T1$ and $T2.$$\begin{array}{clcl} T1: & \text{read (A);} & T2: & \text{read (B);} \\ & \text{read (B);} & & \text{read (A);} \\ ...

18.0k views

commented Dec 31, 2017

0 answers

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Database indexing

500 views

commented Dec 31, 2017

6 answers

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GATE CSE 2014 Set 1 | Question: 28
Consider a selective repeat sliding window protocol that uses a frame size of $1$ $\text{KB}$ to send data on a $1.5$ $\text{Mbps}$ link with a one-way latency of $50$ $\text{msec}$. To achieve a link utilization of $60\%$, the minimum number of bits required to represent the sequence number field is ________.

Consider a selective repeat sliding window protocol that uses a frame size of $1$ $\text{KB}$ to send data on a $1.5$ $\text{Mbps}$ link with a one-way latency of $50$ $\...

27.2k views

commented Nov 10, 2017

15 answers

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GATE CSE 2003 | Question: 78
A processor uses $2-level$ page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $32$ bits wide. The memory is byte addressable. For virtual to physical address translation, the ... virtual address is approximately (to the nearest $0.5$ ns) $1.5$ ns $2$ ns $3$ ns $4$ ns

A processor uses $2-level$ page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addres...

50.0k views

commented Oct 19, 2017

1 answer

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GATE CSE 1991 | Question: 02-iii
Match the pairs in the following questions by writing the corresponding letters only. ...

Match the pairs in the following questions by writing the corresponding letters only.$$\begin{array}{|ll|ll|}\hline \text{(a)} & \text{Buddy system} & \text{(p)} & \tex...

5.8k views

commented Oct 18, 2017

3 answers

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sizeof()
please verify int main() { char a[] = "GATE IITR"; char *b = "GATE IITR"; printf("\n %d %d",sizeof(a),sizeof(b)); printf("\n %d %d",sizeof(*a),sizeof(*b)); } My output 10 9 1 1

please verify int main() { char a[] = "GATE IITR"; char *b = "GATE IITR"; printf("\n %d %d",sizeof(a),sizeof(b)); printf("\n %d %d",sizeof(*a),sizeof(*b)); }My output10 9...

950 views

commented Oct 17, 2017

3 answers

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GATE CSE 2014 Set 3 | Question: 32
An operating system uses shortest remaining time first scheduling algorithm for pre-emptive scheduling of processes. Consider the following set of processes with their arrival times and CPU burst times (in milliseconds): ... The average waiting time (in milliseconds) of the processes is ______.

An operating system uses shortest remaining time first scheduling algorithm for pre-emptive scheduling of processes. Consider the following set of processes with their ar...

9.2k views

commented Oct 14, 2017

8 answers

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GATE CSE 2017 Set 1 | Question: 50
Instruction execution in a processor is divided into $5$ stages, Instruction Fetch (IF), Instruction Decode (ID), Operand fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10 and 3 nanoseconds (ns) ... speedup (correct to two decimal places) achieved by EP over NP in executing $20$ independent instructions with no hazards is _________ .

Instruction execution in a processor is divided into $5$ stages, Instruction Fetch (IF), Instruction Decode (ID), Operand fetch (OF), Execute (EX), and Write Back (WB). T...

19.1k views

commented Sep 18, 2017

3 answers

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GATE IT 2004 | Question: 48
Consider a fully associative cache with $8$ cache blocks (numbered $0-7$) and the following sequence of memory block requests: $4, 3, 25, 8, 19, 6, 25, 8, 16, 35, 45, 22, 8, 3, 16, 25, 7$ If LRU replacement policy is used, which cache block will have memory block $7$? $4$ $5$ $6$ $7$

Consider a fully associative cache with $8$ cache blocks (numbered $0-7$) and the following sequence of memory block requests:$4, 3, 25, 8, 19, 6, 25, 8, 16, 35, 45, 22, ...

15.0k views

commented Sep 15, 2017

4 answers

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GATE CSE 2014 Set 2 | Question: 32
Three processes $A$, $B$ and $C$ each execute a loop of $100$ iterations. In each iteration of the loop, a process performs a single computation that requires $t_c$ CPU milliseconds and then initiates a single I/O operation that lasts ... slice of $50$ milliseconds. The time in milliseconds at which process C would complete its first I/O operation is ___________.

Three processes $A$, $B$ and $C$ each execute a loop of $100$ iterations. In each iteration of the loop, a process performs a single computation that requires $t_c$ CPU m...

12.3k views

commented Sep 12, 2017

6 answers

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GATE IT 2006 | Question: 50
Which one of the choices given below would be printed when the following program is executed? #include <stdio.h> void swap (int *x, int *y) { static int *temp; temp = x; x = y; y = temp; } void printab () { static int i, a = -3, b = -6; i = 0; while (i <= 4) { if ((i++)%2 == 1 ... $a = 12, b = 9$ $a = 3, b = 6$ $a = 3, b = 6$ $a = 6, b = 3$ $a = 15, b = 12$

Which one of the choices given below would be printed when the following program is executed?#include <stdio.h void swap (int *x, int *y) { static int *temp; temp = x; x ...

25.6k views

commented Sep 8, 2017

0 answers

19

Can anyone explain DFS traversal using stack using recursion ?

206 views

asked Aug 31, 2017

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title	title:apple
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score	score:10
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