Login
Register
Dark Mode
Brightness
Profile
Edit Profile
Messages
My favorites
My Updates
Logout
Filter
Profile
Wall
Recent activity
All questions
All answers
Exams Taken
All Blogs
Recent activity by iamhusayn
2
answers
1
GATE Overflow | Programming | Test 1 | Question: 1
What will be the output of the following C program? #include <stdio.h> int main() { int f1(int,int); int x = 9,n = 3; printf("%d", f1(x, n)); } int f1(int x, int n) { int y = 1,i = 1; for(i = 1;i <= n; i++) y = y * x; return(y); } 27 729 81 Compilation Error
What will be the output of the following C program?#include <stdio.h int main() { int f1(int,int); int x = 9,n = 3; printf("%d", f1(x, n)); } int f1(int x, int n) { int y...
1.3k
views
commented
Dec 15, 2016
Programming in C
go-programming-1
programming
programming-in-c
+
–
3
answers
2
direct mapping and types of misses
Consider a cache as follows: Direct mapped 8 words total cache data size 2 words block size A sequence of eight memory read is performed in the order shown from the following addresses: 0 , 11 , 4 , 14 , 9 , 1 , 8 , 0 Calculate No. of misses No of compulsory misses No. of conflict misses No. of capacity misses
Consider a cache as follows:Direct mapped8 words total cache data size2 words block sizeA sequence of eight memory read is performed in the order shown from the following...
6.4k
views
commented
Dec 14, 2016
CO and Architecture
direct-mapping
misses
cache-memory
co-and-architecture
+
–
6
answers
3
GATE CSE 2014 Set 3 | Question: 44
The memory access time is $1$ nanosecond for a read operation with a hit in cache, $5$ nanoseconds for a read operation with a miss in cache, $2$ nanoseconds for a write operation with a hit in cache and $10$ nanoseconds for a write ... cache hit-ratio is $0.9$. The average memory access time (in nanoseconds) in executing the sequence of instructions is ______.
The memory access time is $1$ nanosecond for a read operation with a hit in cache, $5$ nanoseconds for a read operation with a miss in cache, $2$ nanoseconds for a write ...
24.1k
views
commented
Dec 4, 2016
CO and Architecture
gatecse-2014-set3
co-and-architecture
cache-memory
numerical-answers
normal
+
–
4
answers
4
GATE CSE 2016 Set 1 | Question: 51
Consider the following two phase locking protocol. Suppose a transaction $T$ accesses (for read or write operations), a certain set of objects $\{O_1,\ldots,O_k \}$. This is done in the following ... freedom guarantee neither serializability nor deadlock-freedom guarantee serializability but not deadlock-freedom guarantee deadlock-freedom but not serializability.
Consider the following two phase locking protocol. Suppose a transaction $T$ accesses (for read or write operations), a certain set of objects $\{O_1,\ldots,O_k \}$. This...
21.5k
views
answered
Nov 23, 2016
Databases
gatecse-2016-set1
databases
transaction-and-concurrency
normal
+
–
Email or Username
Show
Hide
Password
I forgot my password
Remember
Log in
Register