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3 answers
1
A multi-user, multi-processing operating system cannot be implemented on hardware that does not support Address translation DMA for disk transfer At least two modes of CPU execution (privileged and non-privileged) Demand paging
answer edited Dec 2, 2018 in Operating System 5.7k views
3 answers
2
Which one of the following statements is true? Macro definitions cannot appear within other macro definitions in assembly language programs Overlaying is used to run a program which is longer than the address space of a computer Virtual memory can be used to accommodate ... longer than the address space of a computer It is not possible to write interrupt service routines in a high level language
edited Dec 2, 2018 in Operating System 2.8k views
1 answer
3
Fill in the blanks: Under paged memory management scheme, simple lock and key memory protection arrangement may still be required if the _________ processors do not have address mapping hardware.
answer edited Dec 2, 2018 in Operating System 2.3k views
7 answers
4
Consider the following proposed solution for the critical section problem. There are $n$ processes : $P_0....P_{n-1}$. In the code, function $\text{pmax}$ returns an integer not smaller than any of its arguments .For all $i,t[i]$ is ... process can be in the critical section at any time The bounded wait condition is satisfied The progress condition is satisfied It cannot cause a deadlock
edited Nov 29, 2018 in Operating System 17.3k views
1 answer
5
A critical section is a program segment which should run in a certain amount of time which avoids deadlocks where shared resources are accessed which must be enclosed by a pair of semaphore operations, $P$ and $V$
edited Nov 21, 2018 in Operating System 3.2k views
3 answers
6
Draw a precedence graph for the following sequential code. The statements are numbered from $S_1$ to $S_6$ $S_1$ read n $S_2$ i := 1 $S_3$ if i > n next $S_4$ a(i) := i+1 $S_5$ i := i+1 $S_6$ next : write a(i) Can this graph be converted to a concurrent program using parbegin-parend construct only?
edited Nov 21, 2018 in Operating System 2k views
2 answers
7
The smallest integer that can be represented by an $8-bit$ number in $2's$ complement form is $-256$ $-128$ $-127$ $0$
answer edited Nov 8, 2018 in Digital Logic 3.6k views
3 answers
8
The number $(123456)_8$ is equivalent to $(A72E)_{16}$ and $(22130232)_4$ $(A72E)_{16}$ and $(22131122)_4$ $(A73E)_{16}$ and $(22130232)_4$ $(A62E)_{16}$ and $(22120232)_4$
edited Nov 8, 2018 in Digital Logic 1.5k views
4 answers
9
Assuming all numbers are in $2’s$ complement representation, which of the following numbers is divisible by $11111011$? $11100111$ $11100100$ $11010111$ $11011011$
answer edited Nov 8, 2018 in Digital Logic 3.4k views
4 answers
10
Sign extension is a step in floating point multiplication signed $16$ bit integer addition arithmetic left shift converting a signed integer from one size to another
answer edited Nov 8, 2018 in Digital Logic 2.7k views
6 answers
11
The number of $1$'s in the binary representation of $(3*4096 + 15*256 + 5*16 + 3)$ are: $8$ $9$ $10$ $12$
edited Nov 7, 2018 in Digital Logic 8.6k views
5 answers
12
Consider the number given by the decimal expression: $16^3*9 + 16^2*7 + 16*5+3$ The number of $1’s$ in the unsigned binary representation of the number is ______
answer edited Nov 7, 2018 in Digital Logic 2.1k views
3 answers
13
Which one of the following circuits is NOT equivalent to a $2$-input $XNOR$ (exclusive $NOR$) gate?
answer edited Nov 6, 2018 in Digital Logic 2.2k views
1 answer
14
The following bit pattern represents a floating point number in IEEE $754$ single precision format $1 \ 10000011 \ 101000000000000000000000$ The value of the number in decimal form is $-10$ $-13$ $-26$ None of the above
edited Nov 6, 2018 in Digital Logic 3.3k views
4 answers
15
Which of the following sets of component(s) is/are sufficient to implement any arbitrary Boolean function? XOR gates, NOT gates $2$ to $1$ multiplexers AND gates, XOR gates Three-input gates that output $(A.B) + C$ for the inputs $A, B$ and $C$.
edited Nov 6, 2018 in Digital Logic 7.2k views
9 answers
16
The n-bit fixed-point representation of an unsigned real number $X$ uses $f$ bits for the fraction part. Let $i = n-f$. The range of decimal values for $X$ in this representation is $2^{-f}$ to $2^{i}$ $2^{-f}$ to $\left ( 2^{i} - 2^{-f} \right )$ 0 to $2^{i}$ 0 to $\left ( 2^{i} - 2^{-f} \right )$
answer edited Nov 4, 2018 in Digital Logic 7.3k views
2 answers
17
How many pulses are needed to change the contents of a $8$-bit up counter from $10101100$ to $00100111$ (rightmost bit is the LSB)? $134$ $133$ $124$ $123$
edited Nov 4, 2018 in Digital Logic 2.9k views
1 answer
18
The number of flip-flops required to construct a binary modulo $N$ counter is __________
answer edited Nov 4, 2018 in Digital Logic 2.4k views
2 answers
19
A logic network has two data inputs $A$ and $B$, and two control inputs $C_0$ and $C_1$. It implements the function $F$ according to the following table. ${\begin{array}{|cc|c|}\hline \textbf{$C_1$}& \textbf{$C_2$}& \textbf{F}\\\hline 0&0&\text{$ ... using one $4$ to $1$ Multiplexer, one $2-$input Exclusive OR gate, one $2-$input AND gate, one $2-$input OR gate and one Inverter.
answer edited Nov 1, 2018 in Digital Logic 1.5k views
5 answers
20
How many $3$-to-$8$ line decoders with an enable input are needed to construct a $6$-to-$64$ line decoder without using any other logic gates? $7$ $8$ $9$ $10$
edited Nov 1, 2018 in Digital Logic 9.1k views
5 answers
21
The above synchronous sequential circuit built using JK flip-flops is initialized with $Q_2Q_1Q_0 = 000$. The state sequence for this circuit for the next $3$ clock cycles is $001, 010, 011$ $111, 110, 101$ $100, 110, 111$ $100, 011, 001$
edited Nov 1, 2018 in Digital Logic 5.6k views
5 answers
22
What is the final value stored in the linear feedback shift register if the input is $101101$? $0110$ $1011$ $1101$ $1111$
answer edited Nov 1, 2018 in Digital Logic 2.5k views
3 answers
23
In a look-ahead carry generator, the carry generate function $G_i$ and the carry propagate function $P_i$ for inputs $A_i$ and $B_i$ are given by: $P_i = A_i \oplus B_i \text{ and }G_i = A_iB_i$ The expressions for the sum bit $S_i$ and the carry bit $C_{i+1}$ of the look ahead carry ... 4-bit adder with $S_3, S_2, S_1, S_0$ and $C_4$ as its outputs are respectively: $6, 3$ $10, 4$ $6, 4$ $10, 5$
edited Oct 29, 2018 in Digital Logic 4.9k views
2 answers
24
Booth’s algorithm for integer multiplication gives worst performance when the multiplier pattern is 101010 ….. 1010 100000 ….. 0001 111111 ….. 1111 011111 ….. 1110
answer edited Oct 29, 2018 in Digital Logic 2.8k views
5 answers
25
A Boolean formula is said to be a $tautology$ if it evaluates to TRUE for all assignments to its variables. Which one of the following is NOT a tautology? $(( p \vee q) \wedge (r \vee s)) \Rightarrow (( p \wedge r) \vee q \vee s)$ ... $(( p \vee q ) \wedge ( r \vee s)) \Rightarrow ( p \vee q)$
answer edited Oct 29, 2018 in Digital Logic 644 views
3 answers
26
The Boolean expression $A \oplus B \oplus A$ is equivalent to $AB + \bar {A}\bar B$ $\bar{A}B+A\bar{B}$ $B$ $\bar{A}$
answer edited Oct 26, 2018 in Digital Logic 1.2k views
1 answer
27
Let * be defined as x*y= x'+y. Let z = x*y. Value of z*x is (a) x +y (b) x (c) 0 (d) 1
answer edited Oct 26, 2018 in Digital Logic 2k views
5 answers
28
The simultaneous equations on the Boolean variables $x, y, z$ and $w$, $x + y + z = 1 $ $xy = 0$ $xz + w = 1$ $xy + \bar{z}\bar{w} = 0$ have the following solution for $x, y, z$ and $w,$ respectively: $0 \ 1 \ 0 \ 0$ $1 \ 1 \ 0 \ 1$ $1 \ 0 \ 1 \ 1$ $1 \ 0 \ 0 \ 0$
edited Oct 26, 2018 in Digital Logic 2.8k views
4 answers
29
The number of full and half-adders required to add $16$-bit numbers is $8$ half-adders, $8$ full-adders $1$ half-adder, $15$ full-adders $16$ half-adders, $0$ full-adders $4$ half-adders, $12$ full-adders
edited Oct 22, 2018 in Digital Logic 7.6k views
5 answers
30
An N-bit carry lookahead adder, where $N$ is a multiple of $4$, employs ICs $74181$ ($4$ bit ALU) and $74182$ ( $4$ bit carry lookahead generator). The minimum addition time using the best architecture for this adder is proportional to $N$ proportional to $\log N$ a constant None of the above
edited Oct 22, 2018 in Digital Logic 4.1k views
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