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1

Interrupt
GATE -2009 A CPU generally handles an interrupt by executing an interrupt service routine As soon as an interrupt is raised. By checking the interrupt register at the end of fetch cycle. By checking the interrupt register after finishing the execution of the ... am having confusion between option A and C... For hardware interrupt option A is suitable and for software interrupt option C

commented in CO and Architecture Jan 15, 2021

2.2k views

5 answers

2

127 loopback address question
till which layer the loopback packet goes . i mean to ask that the lowest layer till which packet travel and then come back. I read that it goes to data link layer . but is the point to send it to data link layer as the address 127 is know at ... as the address 127 will be known . which is know at network layer . so i m confussed till which point the packet will go .

commented in Computer Networks Dec 2, 2020

1.4k views

14 answers

3

GATE CSE 2014 Set 1 | Question: 39
The minimum number of comparisons required to find the minimum and the maximum of $100$ numbers is ________

commented in Algorithms Oct 9, 2020

45.2k views

4 answers

4

GATE CSE 2020 | Question: 18
Let $G$ be a group of $35$ elements. Then the largest possible size of a subgroup of $G$ other than $G$ itself is _______.

commented in Set Theory & Algebra Sep 26, 2020

6.4k views

2 answers

5

GATE CSE 1987 | Question: 1-xii
A context-free grammar is ambiguous if: The grammar contains useless non-terminals. It produces more than one parse tree for some sentence. Some production has two non terminals side by side on the right-hand side. None of the above.

commented in Theory of Computation Sep 20, 2020

10.9k views

3 answers

6

Doubt [Graph Theory]
Is it possible that a disconnected graph be an Euler graph ?

answered in Graph Theory Sep 17, 2020

1.3k views

4 answers

7

NIELIT 2017 July Scientist B (CS) - Section B: 11
Consider the following graph $L$ and find the bridges,if any. No bridge $\{d,e\}$ $\{c,d\}$ $\{c,d\}$ and $\{c,f\}$

commented in Graph Theory Sep 16, 2020

864 views

1 answer

8

NIELIT 2016 DEC Scientist B (CS) - Section B: 5
Let $G$ be a simple undirected planar graph on $10$ vertices with $15$ edges. If $G$ is a connected graph, then the number of bounded faces in any embedding of $G$ on the plane is equal to: $3$ $4$ $5$ $6$

commented in Graph Theory Sep 16, 2020

876 views

1 answer

9

Cyclic Prime Implicant K-map
Hi Guys, Any justification for the mentioned answer or what could be the answer ?

commented in Digital Logic Sep 13, 2020

4.2k views

5 answers

10

Size of Virtual Memory - MCQs in CS - Williams
The size of virtual memory is limited by data bus main memory address bus none of the above

commented in Operating System Sep 9, 2020

7.7k views

2 answers

11

MadeEasy Test Series: Programming & DS - Stack
My doubt : What should we consider ^ operator as Bitwise XOR ? or Exponentiation

commented in DS Aug 29, 2020

780 views

6 answers

12

GATE CSE 2008 | Question: 73
Consider a machine with a $2$-way set associative data cache of size $64$ Kbytes and block size $16$ bytes. The cache is managed using $32$ bit virtual addresses and the page size is $4$ Kbytes. A program to be run on this machine begins as follows: double ARR[ ... to array $\text{ARR}$. The cache hit ratio for this initialization loop is: $0\%$ $25\%$ $50\%$ $75\%$

commented in CO and Architecture Jul 15, 2020

6.4k views

3 answers

13

ISRO2020-1
The immediate addressing mode can be used for Loading internal registers with initial values Perform arithmetic or logical operation on data contained in instructions Which of the following is true? Only $1$ Only $2$ Both $1$ and $2$ Immediate mode refers to data in cache

commented in CO and Architecture May 10, 2020

1.8k views

0 answers

14

ISI2014-DCG-70
For the matrices $A = \begin{pmatrix} a & a \\ 0 & a \end{pmatrix}$ and $B = \begin{pmatrix} 0 & 1 \\ -1 & 0 \end{pmatrix}$, $(B^{-1}AB)^3$ is equal to $\begin{pmatrix} a^3 & a^3 \\ 0 & a^3 \end{pmatrix}$ ... $\begin{pmatrix} a^3 & 0 \\ 3a^3 & a^3 \end{pmatrix}$ $\begin{pmatrix} a^3 & 0 \\ -3a^3 & a^3 \end{pmatrix}$

commented in Linear Algebra Jan 3, 2020

279 views

1 answer

15

Number of Topological Order
Find the number of Topological order(sort) in the given graph? $(1)$ $(2)$

commented in DS Oct 23, 2019

3.9k views

0 answers

16

Complementary Number Systems
If N = 670 in base 9 system. Then find the radix complement of N.

commented in Digital Logic Sep 23, 2019

715 views

0 answers

17

MadeEasy Subject Test 2019: Digital Logic - Number Systems
Even after seeing the solution I was unable to understand this question: Can any one tell whats happening here:

commented in Digital Logic Sep 23, 2019

344 views

7 answers

18

GATE CSE 2019 | Question: 40
Consider the following statements: The smallest element in a max-heap is always at a leaf node The second largest element in a max-heap is always a child of a root node A max-heap can be constructed from a binary search tree in $\Theta(n)$ time A binary search tree ... time Which of the above statements are TRUE? I, II and III I, II and IV I, III and IV II, III and IV

commented in DS Sep 16, 2019

15.5k views

4 answers

19

GATE CSE 1992 | Question: 01-vi
In an $11$-bit computer instruction format, the size of address field is $4$-bits. The computer uses expanding OP code technique and has $5$ two-address instructions and $32$ one-address instructions. The number of zero-address instructions it can support is ________

commented in CO and Architecture Sep 8, 2019

10.9k views

1 answer

20

instruction cycle
question A microprocessor provides an instruction capable of moving a string of bytes from one area of memory to another. The fetching and initial decoding of the instruction takes 10 clock cycles.Thereafter, it takes 15 clock cycles to transfer each byte ... cycle becoz control to interrupt will be given when the current instrunction will over and i will over after 970 clock cyle

commented in CO and Architecture Sep 2, 2019

3.9k views

7 answers

21

GATE IT 2008 | Question: 18
How many bytes of data can be sent in $15$ seconds over a serial link with baud rate of $9600$ in asynchronous mode with odd parity and two stop bits in the frame? $10,000$ bytes $12,000$ bytes $15,000$ bytes $27,000$ bytes

commented in Computer Networks Sep 1, 2019

12.8k views

5 answers

22

GATE CSE 2007 | Question: 71
Consider the following program segment. Here $\text{R1, R2}$ and $\text{R3}$ ... word addressable. The number of memory references for accessing the data in executing the program completely is $10$ $11$ $20$ $21$

commented in CO and Architecture Aug 31, 2019

17.7k views

1 answer

23

Question on Relations
A binary relation R on Z × Z is defined as follows: (a, b) R (c, d) iff a = c or b = d Consider the following propositions: 1. R is reflexive. 2. R is symmetric. 3. R is antisymmetric. Which one of the following statements is True?

commented in Set Theory & Algebra Aug 30, 2019

1.7k views

4 answers

24

Minimum number of tables to represent ER-Diagram
The minimum number of tables to represent ER-Diagram such that the relational database satisfies 1NF.

commented in Databases Aug 22, 2019

9.1k views

6 answers

25

GATE CSE 2008 | Question: 77
Delayed branching can help in the handling of control hazards The following code is to run on a pipelined processor with one branch delay slot: I1: ADD $R2 \leftarrow R7 + R8$ I2: Sub $R4 \leftarrow R5 – R6$ ... Which of the instructions I1, I2, I3 or I4 can legitimately occupy the delay slot without any program modification? I1 I2 I3 I4

commented in CO and Architecture Aug 13, 2019

11.0k views

5 answers

26

GATE CSE 2019 | Question: 11
Consider the following two statements about database transaction schedules: Strict two-phase locking protocol generates conflict serializable schedules that are also recoverable. Timestamp-ordering concurrency control protocol with Thomas' Write Rule can generate view serializable ... the above statements is/are TRUE? I only II only Both I and II Neither I nor II

commented in Databases Aug 11, 2019

13.7k views

1 answer

27

Ace Test Series: CO & Architecture - Cache Memory

commented in CO and Architecture Aug 6, 2019

434 views

1 answer

28

Stallings 6e Exercise-11.12 (page no.-539) I/O Management RAID
Consider a 4-drive, 200GB-per-drive RAID array. What is the available data storage capacity for each of the RAID levels, 0, 1, 3, 4, 5, and 6?

commented in Operating System Aug 6, 2019

6.5k views

1 answer

29

Ace Test Series: CO & Architecture - Disk
In the solution to this question, it is given that the number of rotations needed is 2.75. How we got 2.75?

commented in CO and Architecture Aug 6, 2019

764 views

1 answer

30

Ace Test Series: CO & Architecture - Secondary Memory
Consider a disk containing 10 equidistance tracks, the inner track capacity is 20 MB and diameter is 1 cm;

commented in CO and Architecture Aug 6, 2019

305 views