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Recent activity by manisha11

5 answers
1
GATE 2020 CSE | Question: 18
Let $G$ be a group of $35$ elements. Then the largest possible size of a subgroup of $G$ other than $G$ itself is _______.
Let $G$ be a group of $35$ elements. Then the largest possible size of a subgroup of $G$ other than $G$ itself is _______.
commented 4 days ago in Linear Algebra 1.7k views
1 answer
2
GATE1987-1-xii
A context-free grammar is ambiguous if: The grammar contains useless non-terminals. It produces more than one parse tree for some sentence. Some production has two non terminals side by side on the right-hand side. None of the above.
A context-free grammar is ambiguous if: The grammar contains useless non-terminals. It produces more than one parse tree for some sentence. Some production has two non terminals side by side on the right-hand side. None of the above.
commented Sep 20 in Theory of Computation 2.5k views
3 answers
3
Doubt [Graph Theory]
Is it possible that a disconnected graph is an Euler graph ?
Is it possible that a disconnected graph is an Euler graph ?
answered Sep 17 in Algorithms 300 views
3 answers
4
NIELIT 2017 July Scientist B (CS) - Section B: 11
Consider the following graph $L$ and find the bridges,if any. No bridge $\{d,e\}$ $\{c,d\}$ $\{c,d\}$ and $\{c,f\}$
Consider the following graph $L$ and find the bridges,if any. No bridge $\{d,e\}$ $\{c,d\}$ $\{c,d\}$ and $\{c,f\}$
commented Sep 16 in Graph Theory 113 views
1 answer
5
NIELIT 2016 DEC Scientist B (CS) - Section B: 5
Let $G$ be a simple undirected planar graph on $10$ vertices with $15$ edges. If $G$ is a connected graph, then the number of bounded faces in any embedding of $G$ on the plane is equal to: $3$ $4$ $5$ $6$
Let $G$ be a simple undirected planar graph on $10$ vertices with $15$ edges. If $G$ is a connected graph, then the number of bounded faces in any embedding of $G$ on the plane is equal to: $3$ $4$ $5$ $6$
commented Sep 16 in Graph Theory 89 views
1 answer
6
Cyclic Prime Implicant K-map
Hi Guys, Any justification for the mentioned answer or what could be the answer ?
Hi Guys, Any justification for the mentioned answer or what could be the answer ?
commented Sep 13 in Digital Logic 1.9k views
3 answers
9
GATE2008-73
Consider a machine with a $2$-way set associative data cache of size $64$ $Kbytes$ and block size $16$ $bytes$. The cache is managed using $32$ $bit$ virtual addresses and the page size is $4$ $Kbytes$. A program to be run on this machine begins as follows: double ... by the program are those to array $ARR$. The cache hit ratio for this initialization loop is: $0$% $25$% $50$% $75$%
Consider a machine with a $2$-way set associative data cache of size $64$ $Kbytes$ and block size $16$ $bytes$. The cache is managed using $32$ $bit$ virtual addresses and the page size is $4$ $Kbytes$. A program to be run on this machine begins as follows: double ARR[1024 ... made by the program are those to array $ARR$. The cache hit ratio for this initialization loop is: $0$% $25$% $50$% $75$%
commented Jul 15 in CO and Architecture 2.9k views
1 answer
10
ISRO2020-1
The immediate addressing mode can be used for Loading internal registers with initial values Perform arithmetic or logical operation on data contained in instructions Which of the following is true? Only $1$ Only $2$ Both $1$ and $2$ Immediate mode refers to data in cache
The immediate addressing mode can be used for Loading internal registers with initial values Perform arithmetic or logical operation on data contained in instructions Which of the following is true? Only $1$ Only $2$ Both $1$ and $2$ Immediate mode refers to data in cache
commented May 10 in CO and Architecture 399 views
0 answers
11
ISI2014-DCG-70
For the matrices $A = \begin{pmatrix} a & a \\ 0 & a \end{pmatrix}$ and $B = \begin{pmatrix} 0 & 1 \\ -1 & 0 \end{pmatrix}$, $(B^{-1}AB)^3$ is equal to $\begin{pmatrix} a^3 & a^3 \\ 0 & a^3 \end{pmatrix}$ ... $\begin{pmatrix} a^3 & 0 \\ 3a^3 & a^3 \end{pmatrix}$ $\begin{pmatrix} a^3 & 0 \\ -3a^3 & a^3 \end{pmatrix}$
For the matrices $A = \begin{pmatrix} a & a \\ 0 & a \end{pmatrix}$ and $B = \begin{pmatrix} 0 & 1 \\ -1 & 0 \end{pmatrix}$, $(B^{-1}AB)^3$ is equal to $\begin{pmatrix} a^3 & a^3 \\ 0 & a^3 \end{pmatrix}$ $\begin{pmatrix} a^3 & 3a^3 \\ 0 & a^3 \end{pmatrix}$ $\begin{pmatrix} a^3 & 0 \\ 3a^3 & a^3 \end{pmatrix}$ $\begin{pmatrix} a^3 & 0 \\ -3a^3 & a^3 \end{pmatrix}$
commented Jan 3 in Linear Algebra 120 views
1 answer
12
Number of Topological Order
Find the number of Topological order(sort) in the given graph? $(1)$ $(2)$
Find the number of Topological order(sort) in the given graph? $(1)$ $(2)$
commented Oct 23, 2019 in DS 993 views
0 answers
13
Complementary Number Systems
If N = 670 in base 9 system. Then find the radix complement of N.
If N = 670 in base 9 system. Then find the radix complement of N.
commented Sep 23, 2019 in Digital Logic 278 views
7 answers
15
GATE2019-40
Consider the following statements: The smallest element in a max-heap is always at a leaf node The second largest element in a max-heap is always a child of a root node A max-heap can be constructed from a binary search tree in $\theta(n)$ time A binary search tree can be ... time Which of te above statements are TRUE? I, II and III I, II and IV I, III and IV II, III and IV
Consider the following statements: The smallest element in a max-heap is always at a leaf node The second largest element in a max-heap is always a child of a root node A max-heap can be constructed from a binary search tree in $\theta(n)$ time A binary search tree can be constructed ... time Which of te above statements are TRUE? I, II and III I, II and IV I, III and IV II, III and IV
commented Sep 16, 2019 in DS 4.9k views
4 answers
16
GATE1992-01-vi
In an $11-bit$ computer instruction format, the size of address field is $4-bits.$ The computer uses expanding OP code technique and has $5$ two-address instructions and $32$ one-address instructions. The number of zero-address instructions it can support is ________
In an $11-bit$ computer instruction format, the size of address field is $4-bits.$ The computer uses expanding OP code technique and has $5$ two-address instructions and $32$ one-address instructions. The number of zero-address instructions it can support is ________
commented Sep 8, 2019 in CO and Architecture 4.8k views
1 answer
17
instruction cycle
question A microprocessor provides an instruction capable of moving a string of bytes from one area of memory to another. The fetching and initial decoding of the instruction takes 10 clock cycles.Thereafter, it takes 15 clock cycles to transfer each byte ... cycle becoz control to interrupt will be given when the current instrunction will over and i will over after 970 clock cyle
question A microprocessor provides an instruction capable of moving a string of bytes from one area of memory to another. The fetching and initial decoding of the instruction takes 10 clock cycles.Thereafter, it takes 15 clock cycles to transfer each byte.The ... cycle becoz control to interrupt will be given when the current instrunction will over and i will over after 970 clock cyle
commented Sep 2, 2019 in CO and Architecture 1.6k views
6 answers
18
GATE2008-IT-18
How many bytes of data can be sent in $15$ seconds over a serial link with baud rate of $9600$ in asynchronous mode with odd parity and two stop bits in the frame? $10,000$ bytes $12,000$ bytes $15,000$ bytes $27,000$ bytes
How many bytes of data can be sent in $15$ seconds over a serial link with baud rate of $9600$ in asynchronous mode with odd parity and two stop bits in the frame? $10,000$ bytes $12,000$ bytes $15,000$ bytes $27,000$ bytes
commented Sep 1, 2019 in Computer Networks 6.7k views
4 answers
19
GATE2007-71
Consider the following program segment. Here $\text{R1, R2}$ and $\text{R3}$ ... is word addressable. The number of memory references for accessing the data in executing the program completely is $10$ $11$ $20$ $21$
Consider the following program segment. Here $\text{R1, R2}$ and $\text{R3}$ ... that the memory is word addressable. The number of memory references for accessing the data in executing the program completely is $10$ $11$ $20$ $21$
commented Aug 31, 2019 in CO and Architecture 9.3k views
1 answer
20
Question on Relations
A binary relation R on Z × Z is defined as follows: (a, b) R (c, d) iff a = c or b = d Consider the following propositions: 1. R is reflexive. 2. R is symmetric. 3. R is antisymmetric. Which one of the following statements is True?
A binary relation R on Z × Z is defined as follows: (a, b) R (c, d) iff a = c or b = d Consider the following propositions: 1. R is reflexive. 2. R is symmetric. 3. R is antisymmetric. Which one of the following statements is True?
commented Aug 30, 2019 in Set Theory & Algebra 584 views
5 answers
21
Minimum number of tables to represent ER-Diagram
The minimum number of tables to represent ER-Diagram such that the relational database satisfies 1NF.
The minimum number of tables to represent ER-Diagram such that the relational database satisfies 1NF.
commented Aug 22, 2019 in Databases 3.9k views
4 answers
22
GATE2008-77
Delayed branching can help in the handling of control hazards The following code is to run on a pipelined processor with one branch delay slot: I1: ADD $R2 \leftarrow R7 + R8$ I2: Sub $R4 \leftarrow R5 – R6$ I3: ADD $R1 \leftarrow R2 + R3$ ... Which of the instructions I1, I2, I3 or I4 can legitimately occupy the delay slot without any program modification? I1 I2 I3 I4
Delayed branching can help in the handling of control hazards The following code is to run on a pipelined processor with one branch delay slot: I1: ADD $R2 \leftarrow R7 + R8$ I2: Sub $R4 \leftarrow R5 – R6$ I3: ADD $R1 \leftarrow R2 + R3$ I4: STORE ... Which of the instructions I1, I2, I3 or I4 can legitimately occupy the delay slot without any program modification? I1 I2 I3 I4
commented Aug 13, 2019 in CO and Architecture 5.7k views
4 answers
23
GATE2019-11
Consider the following two statements about database transaction schedules: Strict two-phase locking protocol generates conflict serializable schedules that are also recoverable. Timestamp-ordering concurrency control protocol with Thomas' Write Rule can generate view serializable schedules that are ... of the above statements is/are TRUE? I only II only Both I and II Neither I nor II
Consider the following two statements about database transaction schedules: Strict two-phase locking protocol generates conflict serializable schedules that are also recoverable. Timestamp-ordering concurrency control protocol with Thomas' Write Rule can generate view serializable schedules that are not ... Which of the above statements is/are TRUE? I only II only Both I and II Neither I nor II
commented Aug 11, 2019 in Databases 5.6k views
1 answer
25
Stallings 6e Exercise-11.12 (page no.-539) I/O Management RAID
Consider a 4-drive, 200GB-per-drive RAID array. What is the available data storage capacity for each of the RAID levels, 0, 1, 3, 4, 5, and 6?
Consider a 4-drive, 200GB-per-drive RAID array. What is the available data storage capacity for each of the RAID levels, 0, 1, 3, 4, 5, and 6?
commented Aug 6, 2019 in Operating System 570 views
1 answer
26
Ace Test Series: CO & Architecture - Disk
In the solution to this question it is given that the number of rotations needed is 2.75. How we got 2.75?
In the solution to this question it is given that the number of rotations needed is 2.75. How we got 2.75?
commented Aug 6, 2019 in CO and Architecture 319 views
1 answer
28
madeasy testseries cn
<p>Ramesh buy a new laptop, he connected it to Ethernet and after sometime he wishes to surf the internet, so laptop send a DNS request. What will be the sequence of header packet geenrated on request, as it leaves the laptop?</p> <p>udp ... ;/p> <p>Ethernet ip tcp dns</p> <p>udp dns Ethernet ip</p> <p>&nbsp;</p>
<p>Ramesh buy a new laptop, he connected it to Ethernet and after sometime he wishes to surf the internet, so laptop send a DNS request. What will be the sequence of header packet geenrated on request, as it leaves the laptop?</p> <p>udp,dns,ip</p> <p>Ethernet ip udp dns</p> <p>Ethernet ip tcp dns</p> <p>udp dns Ethernet ip</p> <p>&nbsp;</p>
commented Jul 31, 2019 in Computer Networks 416 views
2 answers
29
ME TESTSERIES
If flooding is used to send packets from A to E, then the total number of packets generated in the above network when hop count for A to E is 3 are ________. ANSWER IS 14 .....BUT THE DOUBT IS THAT IS THEIR ANY EFFECT OF SAYING HOP COUNT FOR A TO E BECZ HERE IN 14 WE COUNTED THE HOP OF LENGTH...
If flooding is used to send packets from A to E, then the total number of packets generated in the above network when hop count for A to E is 3 are ________. ANSWER IS 14 .....BUT THE DOUBT IS THAT IS THEIR ANY EFFECT OF SAYING HOP COUNT FOR A TO E BECZ HERE IN 14 WE COUNTED THE HOP OF LENGTH...
commented Jul 31, 2019 in Computer Networks 1k views
2 answers
30
made easy test series
Consider Amit lives in Delhi, connected to the internet via a 100 Mbps connection retrieve a 250 KB webpage from server in Bangalore, where page contain 3 images of 500 KB each. Assume one way propagation delay is 75 ms and Amit's access link is the ... Amit's screen using nonpersistent HTTP and T2 is time using persistent connection, then T = T1 - T2 will be ________ msec.
Consider Amit lives in Delhi, connected to the internet via a 100 Mbps connection retrieve a 250 KB webpage from server in Bangalore, where page contain 3 images of 500 KB each. Assume one way propagation delay is 75 ms and Amit's access link is the bandwidth ... on Amit's screen using nonpersistent HTTP and T2 is time using persistent connection, then T = T1 - T2 will be ________ msec.
commented Jul 30, 2019 in Computer Networks 1.1k views
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