Login
Register
Dark Mode
Brightness
Profile
Edit Profile
Messages
My favorites
My Updates
Logout
Filter
Profile
Wall
Recent activity
All questions
All answers
Exams Taken
All Blogs
Recent activity by manojsahu
3
answers
1
Self doubt
The number of tables required in SELF-REFERENTIAL relation when different mappings(1: M, M:1, 1:1, M: N) are used with different participation (Partial Participation at both sides, Total Participation at both sides and partial participation at one side). (Tabular Format answer will be appreciated).
The number of tables required in SELF-REFERENTIAL relation when different mappings(1: M, M:1, 1:1, M: N) are used with different participation (Partial Participation at b...
6.5k
views
answer edited
Nov 15, 2019
Databases
databases
er-diagram
+
–
6
answers
2
GATE IT 2005 | Question: 76
A company has a class $C$ network address of $204.204.204.0$. It wishes to have three subnets, one with $100$ hosts and two with $50$ ... $204.204.204.128/255.255.255.128$ $204.204.204.64/255.255.255.192$ $204.204.204.0/255.255.255.192$
A company has a class $C$ network address of $204.204.204.0$. It wishes to have three subnets, one with $100$ hosts and two with $50$ hosts each. Which one of the followi...
15.3k
views
commented
Sep 8, 2018
Computer Networks
gateit-2005
computer-networks
subnetting
normal
+
–
6
answers
3
GATE IT 2008 | Question: 41
Assume that a main memory with only $4$ pages, each of $16$ bytes, is initially empty. The CPU generates the following sequence of virtual addresses and uses the Least Recently Used (LRU) page replacement policy. $\text{0, 4, 8, 20, 24, 36, 44, 12, 68, 72, 80, 84, 28, 32, 88, 92}$ How many ... $1, 2, 3, 4$ $7$ and $1, 2, 4, 5$ $8$ and $1, 2, 4, 5$ $9$ and $1, 2, 3, 5$
Assume that a main memory with only $4$ pages, each of $16$ bytes, is initially empty. The CPU generates the following sequence of virtual addresses and uses the Least Re...
23.8k
views
commented
Dec 29, 2017
Operating System
gateit-2008
operating-system
page-replacement
normal
+
–
9
answers
4
GATE CSE 1993 | Question: 6-3
For the initial state of $000$, the function performed by the arrangement of the $\text{J-K}$ flip-flops in figure is: Shift Register $\text{Mod- 3}$ Counter $\text{Mod- 6}$ Counter $\text{Mod- 2}$ Counter None of the above
For the initial state of $000$, the function performed by the arrangement of the $\text{J-K}$ flip-flops in figure is:Shift Register$\text{Mod- 3}$ Counter$\text{Mod- 6}$...
12.6k
views
commented
Dec 27, 2017
Digital Logic
gate1993
digital-logic
sequential-circuit
flip-flop
digital-counter
circuit-output
multiple-selects
+
–
4
answers
5
GATE CSE 1992 | Question: 5-a
The access times of the main memory and the Cache memory, in a computer system, are $500$ n sec and $50$ nsec, respectively. It is estimated that $80\%$ of the main memory request are for read the rest for write. The hit ratio for ... policy (where both main and cache memories are updated simultaneously) is used. Determine the average time of the main memory (in ns).
The access times of the main memory and the Cache memory, in a computer system, are $500$ n sec and $50$ nsec, respectively. It is estimated that $80\%$ of the main memor...
24.0k
views
answered
Dec 23, 2017
CO and Architecture
gate1992
co-and-architecture
cache-memory
normal
numerical-answers
+
–
6
answers
6
GATE CSE 1993 | Question: 11
In the three-level memory hierarchy shown in the following table, $p_i$ denotes the probability that an access request will refer to $M_i$ ... a page swap is $T_i$. Calculate the average time $t_A$ required for a processor to read one word from this memory system.
In the three-level memory hierarchy shown in the following table, $p_i$ denotes the probability that an access request will refer to $M_i$.$$\begin{array}{|c|c|c|c|} \hli...
11.0k
views
answered
Dec 23, 2017
CO and Architecture
gate1993
co-and-architecture
cache-memory
normal
descriptive
+
–
6
answers
7
GATE IT 2007 | Question: 40
What is the final value stored in the linear feedback shift register if the input is $101101$? $0110$ $1011$ $1101$ $1111$
What is the final value stored in the linear feedback shift register if the input is $101101$?$0110$$1011$$1101$$1111$
6.5k
views
answered
Nov 14, 2017
Digital Logic
gateit-2007
digital-logic
circuit-output
normal
+
–
5
answers
8
GATE CSE 1996 | Question: 2.21
Consider the circuit in below figure which has a four bit binary number $b_3b_2b_1b_0$ as input and a five bit binary number, $d_4d_3d_2d_1d_0$ as output. Binary to Hex conversion Binary to BCD conversion Binary to Gray code conversion Binary to $radix-12$ conversion
Consider the circuit in below figure which has a four bit binary number $b_3b_2b_1b_0$ as input and a five bit binary number, $d_4d_3d_2d_1d_0$ as output.Binary to Hex co...
14.0k
views
answered
Nov 12, 2017
Digital Logic
gate1996
digital-logic
circuit-output
normal
+
–
2
answers
9
Random problem
Let A = { a,b,c,d } which of the following is not true ? a) R1 = { (a,a) (c,c) } is Symmetric, Anti-Symmetric and Transitive on A b) R2 = { (a,b) (b,a) (a,c) (c,a) (c,d) } is Symmetric and Anti-Symmetric c) R3 = { (b,c) (c,b) (d,d) } is Symmetric but not Anti-Symmetric d) R4 = { (a,b) (b,c) (c,c) } is Anti-Symmetric but not Symmetric
Let A = { a,b,c,d } which of the following is not true ?a) R1 = { (a,a) (c,c) } is Symmetric, Anti-Symmetric and Transitive on Ab) R2 = { (a,b) (b,a) (a,c) (c,a) (c,d) } ...
290
views
answered
Sep 13, 2017
Set Theory & Algebra
set-theory&algebra
+
–
3
answers
10
Networking-IP
If Direct Broadcast Address of subnet is 201.15.16.31. Which of the following will be subnet mask ? 1. 255.255.255.240 2. 255.255.255.192 3. 255.255.255.198 4. NOTA Explain your answer
If Direct Broadcast Address of subnet is 201.15.16.31. Which of the following will be subnet mask ?1. 255.255.255.2402. 255.255.255.1923. 255.255.255.1984. NOTAExplain yo...
3.7k
views
answered
Aug 8, 2017
Computer Networks
network-addressing
ip-addressing
computer-networks
subnetting
+
–
3
answers
11
Find minimal cover from given functional dependencies
A -> BC CD-> E B->D E->A
A - BCCD- EB->DE->A
8.5k
views
answered
Jul 28, 2017
Databases
database-normalization
decomposition
+
–
1
answer
12
proof
1) Show that when all elements are distinct, the best case running time of HEAPSORT is Ω(n log n). 2) Show that the worst case running time of HEAPSORT is Ω(n log n).
1) Show that when all elements are distinct, the best case running time of HEAPSORT is Ω(n log n).2) Show that the worst case running time of HEAPSORT is Ω(n log n).
2.6k
views
commented
Apr 13, 2017
Algorithms
heap-sort
+
–
Email or Username
Show
Hide
Password
I forgot my password
Remember
Log in
Register