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mohitrai0_0
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Answers by mohitrai0_0
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1
In bellman ford algo why are the no of passes |V|-1 ?
Bellman-ford algo 1) This step initializes distances from source to all vertices as infinite and distance to source itself as 0. Create an array dist[] of size |V| with all values as infinite except dist[src] where src is source vertex. 2) This step ... + weight of edge uv, then update dist[v] .dist[v] = dist[u] + weight of edge uv
Bellman-ford algo 1) This step initializes distances from source to all vertices as infinite and distance to source itself as 0. Create an array dist[] of size |V| with a...
2.1k
views
answered
Mar 22, 2019
Algorithms
bellman-ford
shortest-path
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–
1
votes
2
Master theorem
T(n)=3T(n/4)+nlogn In this if we use master theorem then how is f(n)=Ω(nlog43+ϵ) ?
T(n)=3T(n/4)+nlognIn this if we use master theorem then how is f(n)=Ω(nlog43+ϵ) ?
2.2k
views
answered
Sep 28, 2018
Algorithms
algorithms
master-theorem
asymptotic-notation
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–
5
votes
3
GATE CSE 2016 Set 2 | Question: 31
Consider a processor with $64$ registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and twelve-bit immediate value. Each ... program has $100$ instructions, the amount of memory (in bytes) consumed by the program text is _________.
Consider a processor with $64$ registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers...
20.9k
views
answered
Jul 12, 2018
CO and Architecture
gatecse-2016-set2
instruction-format
machine-instruction
co-and-architecture
normal
numerical-answers
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0
votes
4
GATE CSE 2005 | Question: 80
Consider the following data path of a $\text{CPU}.$ The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including incrementation of the $\text{PC}$ and the $\text{GPRs}$ are to be carried out in ... $2$ $3$ $4$ $5$
Consider the following data path of a $\text{CPU}.$The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including increm...
23.9k
views
answered
Jul 9, 2018
CO and Architecture
co-and-architecture
normal
gatecse-2005
data-path
machine-instruction
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–
8
votes
5
GATE CSE 2005 | Question: 79
Consider the following data path of a $\text{CPU}.$ The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including incrementation of the $\text{PC}$ and the $\text{GPRs}$ are to be carried out in the ... $2$ $3$ $4$ $5$
Consider the following data path of a $\text{CPU}.$The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including increm...
24.1k
views
answered
Jul 9, 2018
CO and Architecture
gatecse-2005
co-and-architecture
machine-instruction
data-path
normal
+
–
17
votes
6
GATE CSE 2015 Set 2 | Question: 25
A computer system implements a $40\;\text{-bit}$ virtual address, page size of $8\;\text{kilobytes}$, and a $128\text{-entry}$ translation look-aside buffer $\text{(TLB)}$ organized into $32$ sets each having $4$ ways. Assume that the $\text{TLB}$ tag does not store any process id. The minimum length of the $\text{TLB}$ tag in bits is ______.
A computer system implements a $40\;\text{-bit}$ virtual address, page size of $8\;\text{kilobytes}$, and a $128\text{-entry}$ translation look-aside buffer $\text{(TLB)}...
21.4k
views
answered
Feb 1, 2018
Operating System
gatecse-2015-set2
operating-system
virtual-memory
easy
numerical-answers
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