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Answers by mystylecse

1 votes
1
Proof of whether a TM accepts epsilon is semi decidable
From rice theorem, I know that it is not recursive. But can someone prove that ? Or atleast give some intuitive proof?
From rice theorem, I know that it is not recursive. But can someone prove that ? Or atleast give some intuitive proof?
0 votes
2
Turing machines decidability
Check whether the language below is recursive, recursively enumerable but not recursive, or not recursively enumerable? {⟨M1,M2⟩∣ M1 and M2 are two TMs, and ϵ∈L(M1)∖L(M2)}.
Check whether the language below is recursive, recursively enumerable but not recursive, or not recursively enumerable?{⟨M1,M2⟩∣ M1 and M2 are two TMs, and ϵ∈L(M...
1 votes
6
decidability
A = { <M> | M is a DFA that accepts some string with more 1s than 0s }. Then A is - a) undecidable b) recursive enumerable c) decidable d) none of the above
A = { <M | M is a DFA that accepts some string with more 1s than 0s }. Then A is - a) undecidable b) recursive enumerablec) decidabled) none of the above
1 votes
7
decidability
E={<M> | M is a TM and L(M)=Φ}. Is E Turing-recognizable?
E={<M | M is a TM and L(M)=Φ}. Is E Turing-recognizable?
3 votes
12
CN Slow Start Throughput
R.T.T=10 microsec. M.S.S=100 Bytes Slow start protocol used to send data.Sender needs to send data till it completes sending window size 8MSS.Find:- a. Total Time taken b. Throughput for 1st RTT c. Total Throughput d. Average Throughput
R.T.T=10 microsec.M.S.S=100 BytesSlow start protocol used to send data.Sender needs to send data till it completes sending window size 8MSS.Find:-a. Total Time takenb....
3 votes
13
Cn: Optimal windows size
The round trip delay between x and y is given as 60 ms and bandwidth of link between X and Y is 512 KBps. What is the optimal window size (in packets) if the packet size is 64 bytes and channel is full duplex
The round trip delay between x and y is given as 60 ms and bandwidth of link between X and Y is 512 KBps. What is the optimal window size (in packets) if the packet size...
0 votes
14
test book test
46 bit Virtual addressing system uses 3 level paging. The page table entry is 32 bits. Size of Page Table is equal to 1 page. The processor uses 1 MB, 16 way set associative cache with 64 block. What is the size of Page Table? a) 2KB b) 4KB c) 8KB d) 16KB
46 bit Virtual addressing system uses 3 level paging. The page table entry is 32 bits. Size of Page Table is equal to 1 page. The processor uses 1 MB, 16 way set associat...
0 votes
17
Permutations
How many different words of 3 length can be formed from a,e,i,o,u containing a,e ?
How many different words of 3 length can be formed from a,e,i,o,u containing a,e ?
0 votes
23
ISRO-2013-14
A processor is fetching instructions at the rate of $1$ MIPS. A DMA module is used to transfer characters to RAM from a device transmitting at $9600$ bps. How much time will the processor be slowed down due to DMA activity? $9.6$ms $4.8$ms $2.4$ms $1.2$ms
A processor is fetching instructions at the rate of $1$ MIPS. A DMA module is used to transfer characters to RAM from a device transmitting at $9600$ bps. How much time w...
1 votes
24
dma throughput
A DMA controller transfers $16$ bytes to memory using cycle stealing with frequency $1.2$GHz. The number of clock cycles used for transfer of $16$ bytes is $20$ Clock cycles. Find the throughout?
A DMA controller transfers $16$ bytes to memory using cycle stealing with frequency $1.2$GHz. The number of clock cycles used for transfer of $16$ bytes is $20$ Clock cyc...
4 votes
25
GATE CSE 1993 | Question: 6.8
The details of an interrupt cycle are shown in figure. Given that an interrupt input arrives every $1$ msec, what is the percentage of the total time that the CPU devotes for the main program execution.
The details of an interrupt cycle are shown in figure.Given that an interrupt input arrives every $1$ msec, what is the percentage of the total time that the CPU devote...
6 votes
27
GATE CSE 1987 | Question: 2a
State whether the following statements are TRUE or FALSE In a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive sumultaneously, the microprocessor attends first to the bus request.
State whether the following statements are TRUE or FALSEIn a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive sumultaneously, the micro...
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