search
Log In

Recent activity by resuscitate

2 answers
1
@Arjun sir, I solved it by using the same concept of gate 2003 78,79 ..but techtud marked it as wrong..this qs has only one confusion which is how to use page table walk and tlb update...I used it in the part of L3 ache miss of Tlb miss.. and used this formula ... Tavg ... (L2 hit(cache time) + L2 miss( L3 hit (cache time) + L3 miss(cache time+page table walk and Tlb update )))) Sir,pls check this
commented Jan 29, 2016 in CO and Architecture 628 views
1 answer
2
they have not given the number of cycles taken by ADD/LOAD..i have taken as 1..correct if i am wrong The following sequence of instruction is executed in a basic 5 stage pipelined processor (S1, S2, S3, S4, S5). Assume that data dependency present in ... output is available in 3rd stage. Assume each stage take 1 cycle. What is the number of cycles are saved by using operand forwarding.
commented Jan 28, 2016 in CO and Architecture 284 views
1 answer
3
An unpipelined processor has got the cycle time of 15 ns. Now the processor is pipelined into three stages and 15 ns is divided among three stages as Stage 1: 6 ns Stage 2: 5 ns Stage 3: 4 ns The latch latency is 2 ns. Now the cycle time of new processor will be _______________ ns (integer value only). I think cycle time should be 6 ns. Latch latency should not be added in cycle time.
comment edited Jan 28, 2016 in CO and Architecture 264 views
1 answer
4
Consider the undirected graph G defined as follows. The vertices are bit string of length 5. We have an edge between vertex “a” and vertex “b” iff “a” and “b” differ only in one bit possible (i.e., hamming distance1). What is the ratio of chromatic number of G to the diameter of G? Model Question : https://gateoverflow.in/3564/gate2006-it_25
commented Jan 28, 2016 in Graph Theory 1.3k views
2 answers
5
Suppose that in $250$ memory references, there are $30$ misses in first level cache and $10$ misses in second level cache. Assume that miss penalty from the L2 cache memory $50$ cycles. The hit time of L2 cache is $10$ cycles. The hit time of the L1 ... $1.25$ memory references per instruction, then the average stall cycles per instruction is ________. answer given is $4$
answered Jan 27, 2016 in CO and Architecture 217 views
3 answers
6
Hit ratio of the cache memory read request is 85% and the cache memory is 5 times faster than main memory. Block size in memory organization is 4 words. The access time of the main memory is 72 ns per word. Write through protocol (simultaneous memory ... remaining for write operation. What is the average access time (in ns) of the memory when considering both read and write operations?
commented Jan 27, 2016 in CO and Architecture 1.2k views
1 answer
7
10 answers
8
A processor uses $2-level$ page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $32$ bits wide. The memory is byte addressable. For virtual to physical address translation, the $10$ most ... access a virtual address is approximately (to the nearest $0.5$ ns) $1.5$ ns $2$ ns $3$ ns $4$ ns
commented Jan 27, 2016 in Operating System 17.6k views
5 answers
10
In an unweighted, undirected connected graph, the shortest path from a node $S$ to every other node is computed most efficiently, in terms of time complexity, by Dijkstra’s algorithm starting from $S$. Warshall’s algorithm. Performing a DFS starting from $S$. Performing a BFS starting from $S$.
commented Jan 27, 2016 in Algorithms 6.3k views
2 answers
11
Arjun sir please help.
commented Jan 24, 2016 in Algorithms 100 views
2 answers
12
Let L = {(aP)*⎪P is a prime number} and Σ={a}. The minimum number of states in NFA that accepts the language L are ________. i don't think it is even a regular language. then how can NFA be generated?
answered Jan 21, 2016 in Theory of Computation 283 views
4 answers
13
9 answers
15
answered Jan 15, 2016 in Computer Networks 1.6k views
1 answer
16
Fill in the blanks Consider the $SDTS$ below $E1\rightarrow E \ out (*2)$ $E \rightarrow +T \ out('1')$ $E \rightarrow T \ out (10^*)$ $E \rightarrow T*F \ out ( ' * ' )$ $T \rightarrow F \ out ('100+')$ ... expression . The value obtained is _____________. Ans =2200 correct ans 2212 I am not getting the answer, plz help. [SDT tracing by default is left-recursive, right??]
commented Jan 14, 2016 in Compiler Design 348 views
1 answer
18
it is very confusing in upper part,someone xplain in details
commented Jan 14, 2016 in Compiler Design 335 views
0 answers
19
how to approach
asked Jan 14, 2016 in Computer Networks 59 views
1 answer
20
An application uses UDP to send 7300 bytes of data in a single message on a path with MTU 1500 and there is an error in one of the datagrams transmitted. The application is a reliable one and so retransmits the data again. If the same application is written ... UDP and there is an error in one of the datagrams transmitted, what is the difference in bytes retransmitted using UDP as compared to TCP
asked Jan 14, 2016 in Digital Logic 254 views
1 answer
21
Let a file of 16 GB has to be transferrred from host A to host B. Assume an MSS size of 2048B. Then what is maximum number of segments that can be transferred such that TCP sequence no don't get exhausted.Assume TCP sequence field 32 bits a)2^21 b)2^23 c)2^11 d)none
answered Jan 13, 2016 in Computer Networks 115 views
0 answers
23
If TCP round trip time is currently 20 ms and ACK comes in after 30 ms then what is the timeout period for next transmission . Use α=0.9 and β=2
commented Jan 13, 2016 in Computer Networks 450 views
1 answer
25
Consider the following function: void f(int a) { if(a <= 0) return ; else{ printf("%d ",a); f(a-2); printf("%d ",a); f(a-3); } } The sum of all values printed by f(6) is _____ .
commented Jan 12, 2016 in Programming 298 views
1 answer
26
I think they calculated whole things wrong.. with operand forwarding answer is 9,but they drew wrong diagram..and without answer will be 14.as we can use id stage under wb stage. so answer shoyld be 5. @arjun sir.
commented Jan 12, 2016 in CO and Architecture 334 views
2 answers
27
My answer is coming 0. Please explain.
commented Jan 12, 2016 in Calculus 970 views
6 answers
28
Consider a simplified time slotted MAC protocol, where each host always has data to send and transmits with probability $p$ = $0.2$ in every slot. There is no backoff and one frame can be transmitted in one slot. If more than one host transmits in the same slot, then the transmissions ... support if each host has to be provided a minimum throughput of $0.16$ frames per time slot? $1$ $2$ $3$ $4$
commented Jan 11, 2016 in Computer Networks 6.6k views
1 answer
29
Given a 32 bit processor with 16 MB main memory, 32 KB 4 way set associative on chip cache and block size of 16 words, The number of tag bits in memory address format are : ? Here we will take the length of instruction as 32 bits or 24 ? Why ?
answer edited Jan 11, 2016 in CO and Architecture 109 views
1 answer
30
Is it Conservative 2 Phase locking (C2PL) ? T1 LOCK-X (A) LOCK-S (B) R(A) R(B) W(A) UNLOCK (A) COMMIT UNLOCK (B)
answered Jan 10, 2016 in Databases 824 views
...