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Answers by resuscitate
6
votes
41
Limits 1raise to infinite
$\lim_{x \rightarrow \infty} \left(\frac{x^{2} + 5x +3}{x^{2} + x + 2}\right)^{x}$
$\lim_{x \rightarrow \infty} \left(\frac{x^{2} + 5x +3}{x^{2} + x + 2}\right)^{x}$
450
views
answered
Dec 30, 2015
Calculus
limits
calculus
+
–
2
votes
42
Finding Hit Ratio when memory references are given in Hex
A byte addressable computer has a small data cache capable of holding eight 32 bit words. Each cache block consist of two 32 bit words. For the following sequence of addresses (in hexa decimal ). Find the hit ratio if two way ... is conflicting. You can check it here - https://gateoverflow.in/29182/cache-miss-in-two-way-set-associative ]
A byte addressable computer has a small data cache capable of holding eight 32 bit words. Each cache block consist of two 32 bit words. For the following sequence of addr...
2.3k
views
answered
Dec 30, 2015
CO and Architecture
cache-memory
memory-management
co-and-architecture
+
–
0
votes
43
ISRO2015-53
An ACK number of $1000$ in TCP always means that $999$ bytes have been successfully received $1000$ bytes have been successfully received $1001$ bytes have been successfully received None of the above
An ACK number of $1000$ in TCP always means that$999$ bytes have been successfully received$1000$ bytes have been successfully received$1001$ bytes have been successfully...
8.3k
views
answered
Dec 29, 2015
Computer Networks
isro2015
computer-networks
tcp
+
–
39
votes
44
GATE CSE 1996 | Question: 10
Let $A = \begin{bmatrix} a_{11} && a_{12} \\ a_{21} && a_{22} \end{bmatrix} \text { and } B = \begin{bmatrix} b_{11} && b_{12} \\ b_{21} && b_{22} \end{bmatrix}$ be two matrices such that $AB=I$ ... $CD =I$. Express the elements of $D$ in terms of the elements of $B$.
Let $A = \begin{bmatrix} a_{11} && a_{12} \\ a_{21} && a_{22} \end{bmatrix} \text { and } B = \begin{bmatrix} b_{11} && b_{12} \\ b_{21} && b_{22} \end{bmatrix}$ be two m...
4.0k
views
answered
Dec 26, 2015
Linear Algebra
gate1996
linear-algebra
matrix
normal
descriptive
+
–
3
votes
45
FIND THE NO OF KEYS
Consider relation $r(P, Q, R, S)$ with functional dependencies $PQ \rightarrow R$ $PQ \rightarrow S$ $R \rightarrow P$ $S \rightarrow Q$ Find the number of keys in the relation $R$.
Consider relation $r(P, Q, R, S)$ with functional dependencies$PQ \rightarrow R$$PQ \rightarrow S$$R \rightarrow P$$S \rightarrow Q$Find the number of keys in the relatio...
428
views
answered
Dec 24, 2015
1
votes
46
congestion window
Let the size of congestion window of a TCP connection be 32 KB. When the timeout occurs maximum segment size used is 2 KB. If the time taken by TCP connection to get 32 KB congestion window is 480 msec then the RTT of connection is _________ (in msec).
Let the size of congestion window of a TCP connection be 32 KB. When the timeout occurs maximum segment size used is 2 KB. If the time taken by TCP connection to get 32 K...
1.1k
views
answered
Dec 24, 2015
Computer Networks
congestion-control
computer-networks
+
–
0
votes
47
FIND INHERENTLY AMBIGUOUS GRAMMAR-
1.2k
views
answered
Dec 24, 2015
0
votes
48
how to find path of length 3 in below graph including V5 ?
what is the issue in the given approach ? Since the path should pass through v5 I am assuming we only include the path in which v5 can be intermediate vertex. And path visited in reverse order is not counted as distinct. Let us ... first vertex we can have total of 16 choices. This gives total paths possible as 16. But answer given is 4C3 .
what is the issue in the given approach ?Since the path should pass through v5 I am assuming we only include the path in which v5 can be intermediate vertex.And path visi...
1.5k
views
answered
Dec 21, 2015
Graph Theory
graph-theory
+
–
0
votes
49
Set associative cache
in this question how we can know set associativity. Consider two cache organizations. The first one if 64 KB way associative with 64 byte block size. The second one is of the 64 KB direct mapped cache. The size of an address is 32 bits in ... hit latencies of both cache organizations (i.e. associative hit latency – direct mapped hit latency) (in nsec) is ___________.
in this question how we can know set associativity.Consider two cache organizations. The first one if 64 KB way associative with 64 byte block size. The second one is of ...
1.1k
views
answered
Dec 20, 2015
0
votes
50
If an LL(1) parser carries out the SDT for a string output will be ??
1.1k
views
answered
Dec 20, 2015
Compiler Design
compiler-design
syntax-directed-translation
virtual-gate-test-series
+
–
1
votes
51
Set associative cache
in this question how we can know set associativity. Consider two cache organizations. The first one if 64 KB way associative with 64 byte block size. The second one is of the 64 KB direct mapped cache. The size of an address is 32 bits in ... hit latencies of both cache organizations (i.e. associative hit latency – direct mapped hit latency) (in nsec) is ___________.
in this question how we can know set associativity.Consider two cache organizations. The first one if 64 KB way associative with 64 byte block size. The second one is of ...
1.1k
views
answered
Dec 20, 2015
0
votes
52
Heap Sort
statement is true or false Heap sort is inplace algorithm. it is given as true but heapsort uses maxheapify procedure which requires extra stack ., then how it is inplace..?
statement is true or falseHeap sort is inplace algorithm. it is given as truebut heapsort uses maxheapify procedure which requires extra stack ., then how it is inplac...
547
views
answered
Dec 17, 2015
Algorithms
algorithms
true-false
heap-sort
+
–
5
votes
53
Number of Inversions
A) 192 B) 120 c) 188 D) 176
A) 192 B) 120 c) 188 D) 176
718
views
answered
Dec 16, 2015
Algorithms
algorithms
inversion
insertion-sort
+
–
0
votes
54
Hashing
779
views
answered
Dec 16, 2015
Algorithms
hashing
chaining
probability
numerical-answers
test-series
+
–
0
votes
55
TCP slow start right ans????????????
351
views
answered
Dec 16, 2015
8
votes
56
Computer networks
A group of N stations share 100 Kbps slotted ALOHA channel. Each station output, a 500 bits frame on an average of 5000 ms; even if previous one has not been sent. What is the required value of N?
A group of N stations share 100 Kbps slotted ALOHA channel. Each station output, a 500 bits frame on an average of 5000 ms; even if previous one has not been sent. What i...
15.1k
views
answered
Dec 14, 2015
1
votes
57
Exponential average
in this question alpha =0.25. but how we can determine that alpha
in this question alpha =0.25. but how we can determine that alpha
856
views
answered
Dec 11, 2015
0
votes
58
Test Series QS - Algorithms
When searching for the key value 50 in a binary search tree, node containing the key values 10, 30, 40, 70, 90, 120, 150, 175 are traversed, in any order. The number of different orders passing in which these keys values can occur on the search path from the root to node containing the value 50 are ________.
When searching for the key value 50 in a binary search tree, node containing the key values 10, 30, 40, 70, 90, 120, 150, 175 are traversed, in any order. The number of d...
516
views
answered
Dec 8, 2015
DS
data-structures
binary-search-tree
numerical-answers
made-easy-test-series
+
–
2
votes
59
Stop and wait
if packet size is 1KB and propogation time 15msec, channel capacity 10^9 b/s , find transmission time and sender utilization in stop and wait protocol ?
if packet size is 1KB and propogation time 15msec, channel capacity 10^9 b/s , find transmission time and sender utilization in stop and wait protocol ?
1.3k
views
answered
Dec 8, 2015
0
votes
60
number of WAR dependencies
Consider the following instructions. $I_1:R_1=100$ $I_2:R_1=R_2+R_4$ $I_3:R_2=R_4+25$ $I_4:R_4=R_1+R_3$ $I_5:R_1=R_1+30$ Calculate sum of ($\text{WAR, RAW and WAW}$) dependencies the above instructions. $10$ $12$ $6$ $8$
Consider the following instructions.$I_1:R_1=100$$I_2:R_1=R_2+R_4$$I_3:R_2=R_4+25$$I_4:R_4=R_1+R_3$$I_5:R_1=R_1+30$Calculate sum of ($\text{WAR, RAW and WAW}$) dependenci...
6.7k
views
answered
Dec 7, 2015
CO and Architecture
co-and-architecture
data-dependency
+
–
2
votes
61
how to draw the graph for this problem??
how many numbers of edges if the degree of sequence is 5,2,2,2,2,1.... how can we draw the graph for this problem??? there is any formula for such type of problem???
how many numbers of edges if the degree of sequence is 5,2,2,2,2,1.... how can we draw the graph for this problem??? there is any formula for such type of problem???
893
views
answered
Dec 6, 2015
1
votes
62
check the question
A computer system implements a 8kilobytes pages and a 36 bit physical address space.each page table entry contains a valid bit,and the translation.if the maximum size of the page table is 96megabytes,Then what will be the length of the virtual address supported by the system(in bits)?
A computer system implements a 8kilobytes pages and a 36 bit physical address space.each page table entry contains a valid bit,and the translation.if the maximum size of ...
466
views
answered
Dec 4, 2015
0
votes
63
check the quesion
consider a uniprocess system executing four tasks T1,T2,T3 and T4 each of which is composed of an 10 sequence of job(or instances) which are arrives at periodically at interval of 2,4,8 and 16 ms respectively.the priority of each task is directly ... all task arrive at beginning of the 2ms and task preempted allowed,the 2nd instance of T3 its execution at the end of_______ ms
consider a uniprocess system executing four tasks T1,T2,T3 and T4 each of which is composed of an 10 sequence of job(or instances) which are arrives at periodically at in...
891
views
answered
Dec 4, 2015
4
votes
64
Cache memory(made easy)
During a program execution out of 1000 memory references there are 250 and 120 misses in L1 (Level1) and L2(Level2) caches respectively. Hit times for L1 and L2 cache are 24 and 40 cycles respectively. If there are 2.5 memory references per instruction, how many average stall cycles per instruction? (Assume L2 to memory miss penalty is 250 cycles)? a)50 b)100 c)150 d)200
During a program execution out of 1000 memory references there are 250 and 120 misses in L1 (Level1) and L2(Level2) caches respectively. Hit times for L1 and L2 cache are...
2.2k
views
answered
Nov 28, 2015
0
votes
65
Question on process state transition
Answer to the above question is (C). I am unable to understand that how can a process in ready state can get blocked. Please give an explanation.
Answer to the above question is (C). I am unable to understand that how can a process in ready state can get blocked. Please give an explanation.
3.3k
views
answered
Nov 28, 2015
Operating System
process-scheduling
operating-system
+
–
–1
votes
66
Identify the type of Grammar
The Grammar E$\rightarrow$ EE | a is LR(1) SLR(1) LR(0) None
The Grammar E$\rightarrow$ EE | a isLR(1)SLR(1)LR(0)None
3.8k
views
answered
Nov 20, 2015
Compiler Design
parsing
theory-of-computation
+
–
1
votes
67
explain....
When searching for the key value 50 in a binary search tree, node containing the key values 10, 30, 40, 70, 90, 120, 150, 175 are traversed, in any order. The number of different orders passing in which these keys values can occur on the search path from the root to node containing the value 50 are ________.
When searching for the key value 50 in a binary search tree, node containing the key values 10, 30, 40, 70, 90, 120, 150, 175 are traversed, in any order. The number of d...
397
views
answered
Nov 16, 2015
4
votes
68
GATE CSE 2011 | Question: 31
Given $i = \sqrt{-1}$, what will be the evaluation of the definite integral $\int \limits_0^{\pi/2} \dfrac{\cos x +i \sin x} {\cos x - i \sin x} dx$ ? $0$ $2$ $-i$ $i$
Given $i = \sqrt{-1}$, what will be the evaluation of the definite integral $\int \limits_0^{\pi/2} \dfrac{\cos x +i \sin x} {\cos x - i \sin x} dx$ ?$0$$2$$-i$$i$
10.9k
views
answered
Nov 4, 2015
Calculus
gatecse-2011
calculus
integration
normal
+
–
2
votes
69
OS Gateforum Section test Q2
451
views
answered
Nov 1, 2015
Operating System
test-series
operating-system
+
–
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