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Questions by rishabhdevsingh1
0
votes
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answers
1
pipeline
consider a5 stage pipeline processor, 20% load instructions, 25% branches, 20% stores, 20% of all instructions are data dependent on instructions in front of them and branches are taken 75%of time. what would be the expected cpi?
consider a5 stage pipeline processor, 20% load instructions, 25% branches, 20% stores, 20% of all instructions are data dependent on instructions in front of them and bra...
728
views
asked
Nov 10, 2018
CO and Architecture
co-and-architecture
pipelining
stall
numerical-answers
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0
votes
0
answers
2
adressing modes
For Given machine instructions LW R4 #400 L1:LW R1, 0,(R4) LW R2 400(R4) ADDI R3, R1, R2 SW R3, 0(R4) SUB R4, R4, #4 BNZ R4, L1 on a 5 stage pipeline processor, 1 clock cycle per stage. how mAny clock cycles willtake execution of this segment on the regular architecture?
For Given machine instructionsLW R4 #400L1:LW R1, 0,(R4)LW R2 400(R4)ADDI R3, R1, R2SW R3, 0(R4)SUB R4, R4, #4BNZ R4, L1on a 5 stage pipeline processor, 1 clock cycle per...
631
views
asked
Nov 10, 2018
CO and Architecture
co-and-architecture
machine-instruction
registers
pipelining
addressing-modes
numerical-answers
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–
0
votes
1
answer
3
adressing modes
Given 2 machine instructions, LW R4 #400 LW R1, 0,(R4) IN second instruction what will be loaded in R1,is it the operand at memory location 400?or some random memory location operand..I want to clarify whether the value stored in register is same as adress that register points.
Given 2 machine instructions,LW R4 #400LW R1, 0,(R4)IN second instruction what will be loaded in R1,is it the operand at memory location 400?or some random memory locatio...
1.2k
views
asked
Nov 9, 2018
CO and Architecture
co-and-architecture
machine-instruction
addressing-modes
registers
numerical-answers
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–
0
votes
0
answers
4
Paging
Consider a system with page size 2^13 bytes , a2 level page table organization PTE size 32 bits with following format. Bit0: present bit Bit1:valid bit Bit2:dirty bit Bit6-29: physical frame no. Other bits insignificant. If last level PTE for the virtual address 0x12345678 has value 0x103 and processor trying to read a inst. From that address.what memory address will be read?
Consider a system with page size 2^13 bytes , a2 level page table organization PTE size 32 bits with following format.Bit0: present bitBit1:valid bitBit2:dirty bitBit6-29...
401
views
asked
Oct 31, 2018
Operating System
operating-system
paging
multilevel-paging
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