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Answers by rishi71662data4
0
votes
1
Gatebook mock
Below is a precedence graph for a set of tasks to be executed on a parallel processing system $S$. Efficiency is defined as the ratio between the speedup and the number of processors. (The speedup is defined as the ratio of the time taken to perform a set of tasks on a single ... same time, what is the efficiency of this precedence graph on $S$? $25\%$ $33\:1/3\%$ $50\%$ $100\%$
Below is a precedence graph for a set of tasks to be executed on a parallel processing system $S$. Efficiency is defined as the ratio between the speedup and the number o...
1.6k
views
answered
Jan 16, 2018
CO and Architecture
gatebook-mt2
co-and-architecture
speedup
+
–
3
votes
2
GATE2014 EC-1: GA-10
You are given three coins: one has heads on both faces, the second has tails on both faces, and the third has a head on one face and a tail on the other. You choose a coin at random and toss it, and it comes up heads. The probability that the other face is tails is $\dfrac{1}{4}$ $\dfrac{1}{3}$ $\dfrac{1}{2}$ $\dfrac{2}{3}$
You are given three coins: one has heads on both faces, the second has tails on both faces, and the third has a head on one face and a tail on the other. You choose a coi...
10.3k
views
answered
Dec 14, 2017
Quantitative Aptitude
gate2014-ec-1
quantitative-aptitude
probability
conditional-probability
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–
2
votes
3
GATE2013 AE: GA-10
In a factory, two machines $M1$ and $M2$ manufacture $60\%$ and $40\%$ of the autocomponents respectively. Out of the total production, $2\%$ of $M1$ and $3\%$ of $M2$ are found to be defective. If a randomly drawn autocomponent from the combined lot is found defective, what is the probability that it was manufactured by $M2$? $0.35$ $0.45$ $0.5$ $0.4$
In a factory, two machines $M1$ and $M2$ manufacture $60\%$ and $40\%$ of the autocomponents respectively. Out of the total production, $2\%$ of $M1$ and $3\%$ of $M2$ ar...
5.0k
views
answered
Dec 14, 2017
Quantitative Aptitude
gate2013-ae
quantitative-aptitude
conditional-probability
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–
1
votes
4
computer network
In class C network 3 bits are 3 bits are borrowed for subnetting host id parts.Total possible number of subnet masks are ______ ?
In class C network 3 bits are 3 bits are borrowed for subnetting host id parts.Total possible number of subnet masks are ______ ?
5.4k
views
answered
Oct 24, 2017
Computer Networks
computer-networks
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–
1
votes
5
Decidability property.
Intersection of languages produced by two DCFG is a DCFL . Decidable or not ? Please give reference for your answer.
Intersection of languages produced by two DCFG is a DCFL . Decidable or not ? Please give reference for your answer.
1.7k
views
answered
Oct 23, 2017
Theory of Computation
theory-of-computation
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–
2
votes
6
UGC NET CSE | December 2004 | Part 2 | Question: 34
Which activity is included in the first pass of two pass assemblers? Build the symbol table Construct the intermediate code Separate mnemonic opcode and operand fields None of these
Which activity is included in the first pass of two pass assemblers?Build the symbol tableConstruct the intermediate codeSeparate mnemonic opcode and operand fieldsNone o...
1.9k
views
answered
Oct 22, 2017
Compiler Design
ugcnetcse-dec2004-paper2
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–
1
votes
7
dooubt
due to contiguous allocation we always suffer from external fragmentation // is it right to use word always here ,
due to contiguous allocation we always suffer from external fragmentation // is it right to use word always here ,
459
views
answered
Oct 20, 2017
0
votes
8
computer networks
difference between circuit switching and virtual circuit switching ? do we have icmp in syllabus ?
difference between circuit switching and virtual circuit switching ?do we have icmp in syllabus ?
424
views
answered
Oct 20, 2017
Computer Networks
computer-networks
network
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–
0
votes
9
Os doubt bounded wait
Check the critical section requirement for the following code 1)Int flag[2]= {false,false};// flag[i] indicates that p(i) is in false state. P(i) true then it get into cs while (flag[1-i]); Flag[i]=true; Critical section; Flag [i]= false; 2)Int ... Flag[i]=true; while (flag[1-i]); Critical section; Flag [i]= false; Whether in above code bounded wait is satisfied or not????
Check the critical section requirement for the following code1)Int flag = {false,false};// flag[i] indicates that p(i) is in false state.P(i) true then it get into cswhil...
415
views
answered
Oct 20, 2017
2
votes
10
LOGICAL ADDRESS
Can MAC address ne used as logical address at Network layer ? and can IP address be used as Physical address at DLL ?
Can MAC address ne used as logical address at Network layer ?and can IP address be used as Physical address at DLL ?
837
views
answered
Oct 19, 2017
Computer Networks
computer-networks
+
–
1
votes
11
regular
A) L : {a2n ; n>=0} regular or not? B) Let G1 and G2 are CFG's .... L(G1) intersection L(G2) = $\phi$ is decidable or not
A) L : {a2n ; n>=0} regular or not?B) Let G1 and G2 are CFG's .... L(G1) intersection L(G2) = $\phi$ is decidable or not
439
views
answered
Oct 19, 2017
1
votes
12
Round robin response time.
Response time either increases or remains same if time quantum increases but never decreases. True or false?
Response time either increases or remains same if time quantum increases but never decreases.True or false?
631
views
answered
Oct 19, 2017
Operating System
operating-system
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–
1
votes
13
Self Doubt
Can Someone exlain this "In level triggering circuit the output may change several times in a single clock whereas in a edge triggering circuit the output will change only once in a single clock."
Can Someone exlain this"In level triggering circuit the output may change several times in a single clock whereas in a edge triggering circuit the output will change only...
1.8k
views
answered
Oct 19, 2017
Digital Logic
digital-logic
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–
0
votes
14
test series
Given IP = 210.15.131.141 and subnet mask = 255.255.255.224. Calculate the last host of last subnet? a) 210.15.131.222 b)210.15.131.162 c)210.15.131.202 the answer given is A, but i have a doubt since this is a class C address.. and 224=11100000 we have 3 bits ... 11111 is for DBA .. so acc to me .. the answer should be 210.15.31.254 . where am i going wrong ? someone pls clarify it ..
Given IP = 210.15.131.141 and subnet mask = 255.255.255.224. Calculate the last host of last subnet?a) 210.15.131.222b)210.15.131.162 c)210.15.131.202the answer given is ...
482
views
answered
Oct 18, 2017
0
votes
15
3.Array
Consider a stack is implemented using an array. What is worst case time complexity of push operation? give explanation
Consider a stack is implemented using an array. What is worst case time complexity of push operation?give explanation
641
views
answered
Oct 17, 2017
DS
array
data-structures
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–
3
votes
16
Self doubt
S -> AB | BAB A -> SA | ba B -> a | $\epsilon$ What are the follow of S, A, B?
S - AB | BABA - SA | baB - a | $\epsilon$What are the follow of S, A, B?
323
views
answered
Oct 17, 2017
Compiler Design
compiler-design
first-and-follow
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–
0
votes
17
If PEN – MEN = 87, then BOY – CAN =?
If PEN – MEN = 87, then BOY – CAN = ? (A) 256 (B) 169 (C) 345 (D) 318
If PEN – MEN = 87, then BOY – CAN = ?(A) 256(B) 169(C) 345(D) 318
1.3k
views
answered
Oct 17, 2017
0
votes
18
Indexing
1.0k
views
answered
Oct 16, 2017
Databases
indexing
databases
bplustrees
+
–
16
votes
19
GATE CSE 1999 | Question: 1.20
Booth's coding in $8$ bits for the decimal number $-57$ is: $0-100+1000$ $0-100+100-1$ $0-1+100-10+1$ $00-10+100-1$
Booth's coding in $8$ bits for the decimal number $-57$ is:$0-100+1000$$0-100+100-1$$0-1+100-10+1$$00-10+100-1$
13.3k
views
answered
Oct 16, 2017
Digital Logic
gate1999
digital-logic
number-representation
booths-algorithm
normal
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–
1
votes
20
Aymptotic notation
Consider $\sum_{i=0}^n{}$ i3 =x.what can be X 1.theta(n4) 2.theta(n5) 3.O(n5) 4.$\Omega$(n3)
Consider $\sum_{i=0}^n{}$ i3 =x.what can be X1.theta(n4)2.theta(n5)3.O(n5)4.$\Omega$(n3)
396
views
answered
Oct 15, 2017
Algorithms
asymptotic-notation
multiple-selects
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–
1
votes
21
#Parsing
How to check in the grammar that which parsing method works more efficient for it? For eg in the following grammar - S-> Aa/b S->a Options - a) Top - Down b) Bottom - up c) Both d) None of these Answer is b.
How to check in the grammar that which parsing method works more efficient for it?For eg in the following grammar -S- Aa/bS->aOptions -a) Top - Downb) Bottom - upc) Bothd...
600
views
answered
Oct 7, 2017
Compiler Design
compiler-design
grammar
parsing
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–
0
votes
22
graph - self doubt
Graph G has atleast 1 edge then which are true a) G has a hamiltonian circuit b) Every cycle of G is of even length
Graph G has atleast 1 edge then which are truea) G has a hamiltonian circuitb) Every cycle of G is of even length
314
views
answered
Sep 14, 2017
0
votes
23
number system
what is the probability of overflow occurring in addition of two 3-bit signed 2's complement number?
what is the probability of overflow occurring in addition of two 3-bit signed 2's complement number?
373
views
answered
Sep 14, 2017
0
votes
24
computer network
Suppose that 2 parties A and B wish to setup a common secret key (D-H key) between themselves using the Diffie - Hellman key exchange technique. They agree on 47 as the modulus and 3 as the primitive root . Party A chooses 8 and party B chooses 10 as their respective secrets. Their D-H key is ___________________ A) 3 B) 4 C) 5 D) 6
Suppose that 2 parties A and B wish to setup a common secret key (D-H key) between themselves using the Diffie - Hellman key exchange technique. They agree on 47 as the m...
1.1k
views
answered
Jul 7, 2017
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