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Recent activity by shaktisingh
2
answers
1
TIFR CSE 2019 | Part B | Question: 5
Stirling's approximation for $n!$ states for some constants $c_1,c_2$ $c_1 n^{n+\frac{1}{2}}e^{-n} \leq n! \leq c_2 n^{n+\frac{1}{2}}e^{-n}.$ What are the tightest asymptotic bounds that can be placed on $n!$ $?$ ... $n! =\Theta((\frac{n}{e})^{n+\frac{1}{2}})$ $n! =\Theta(n^{n+\frac{1}{2}}2^{-n})$
Stirling’s approximation for $n!$ states for some constants $c_1,c_2$$$c_1 n^{n+\frac{1}{2}}e^{-n} \leq n! \leq c_2 n^{n+\frac{1}{2}}e^{-n}.$$What are the tightest asym...
3.4k
views
commented
Jan 28, 2020
Algorithms
tifr2019
algorithms
asymptotic-notation
+
–
13
answers
2
Minimum number of tables to represent ER-Diagram
How many minimum relations required for given ER diagram ?
How many minimum relations required for given ER diagram ?
8.8k
views
answered
Jan 25, 2020
Databases
er-diagram
databases
er-to-relational
relational
+
–
4
answers
3
GATE CSE 1992 | Question: 01-vi
In an $11$-bit computer instruction format, the size of address field is $4$-bits. The computer uses expanding OP code technique and has $5$ two-address instructions and $32$ one-address instructions. The number of zero-address instructions it can support is ________
In an $11$-bit computer instruction format, the size of address field is $4$-bits. The computer uses expanding OP code technique and has $5$ two-address instructions and ...
13.2k
views
answered
Jan 23, 2020
CO and Architecture
gate1992
co-and-architecture
machine-instruction
instruction-format
normal
numerical-answers
+
–
3
answers
4
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 9
A byte-addressable computer has a small data cache capable of holding eight $32$-bit words. Each cache block consists of one $32$-bit word. When a given program is executed, the processor reads data from the following ... cache is initially empty. If a direct-mapped cache is used, then the hit rate is __________ $\%$
A byte-addressable computer has a small data cache capable of holding eight $32$-bit words. Each cache block consists of one $32$-bit word. When a given program is execut...
856
views
answered
Jan 18, 2020
CO and Architecture
tbb-coa-1
co-and-architecture
numerical-answers
+
–
4
answers
5
ISRO2020-14
In a two-pass assembler, resolution of subroutine calls and inclusion of labels in the symbol table is done during second pass first pass and second pass respectively second pass and first pass respectively first pass
In a two-pass assembler, resolution of subroutine calls and inclusion of labels in the symbol table is done duringsecond passfirst pass and second pass respectivelysecond...
3.8k
views
commented
Jan 14, 2020
Compiler Design
isro-2020
compiler-design
assembler
easy
+
–
0
answers
6
GATE Overflow | Compiler Design | Test 1 | Parsing | Question: 11
Which of the following is TRUE regarding the running time of a LR(1) parser? It runs in linear time for all inputs It runs in polynomial time but not necessarily $O(n^3)$ for all inputs For some inputs it may take exponential time It runs in $O(n^3)$ but not always $O(n^2)$
Which of the following is TRUE regarding the running time of a LR(1) parser?It runs in linear time for all inputsIt runs in polynomial time but not necessarily $O(n^3)$ f...
2.0k
views
commented
Jan 12, 2020
Compiler Design
go-cd-1
+
–
1
answer
7
GATE CSE 1987 | Question: 8a
Consider the following proposal to the "readers and writers problem." Shared variables and semaphores: aw, ar, rw, rr : interger; mutex, reading, writing: semaphore: initial values of variables and states of semaphores: ar=rr=aw ... group of readers make waiting writers starve? Can writers starve readers? Explain in two sentences why the solution is incorrect.
Consider the following proposal to the "readers and writers problem."Shared variables and semaphores:aw, ar, rw, rr : interger; mutex, reading, writing: semaphore: initia...
3.1k
views
commented
Jan 11, 2020
Operating System
gate1987
operating-system
process-synchronization
descriptive
+
–
1
answer
8
Test by Bikram | Mathematics | Test 2 | Question: 13
With reference to the above diagram: $f$ is onto, $g$ is onto $\implies \: g.f$ is onto. if $g.f$ is one-to-one $\implies \: g$ and $f$ both need to be one-to-one. if $g.f$ is onto $\implies \: g$ has to be ... is bijective Which of the following statements is TRUE? I,II are correct. I,II,III are correct. I,III,IV are correct. I,IV are correct.
With reference to the above diagram:$f$ is onto, $g$ is onto $\implies \: g.f$ is onto.if $g.f$ is one-to-one $\implies \: g$ and $f$ both need to be one-to-one.if $g.f$ ...
320
views
commented
Jan 8, 2020
Mathematical Logic
tbb-mathematics-2
+
–
3
answers
9
UGC NET CSE | December 2019 | Part 2 | Question: 21
Given two tables $R1(x,y)$ and $R2(y,z)$ with $50$ and $30$ number of tuples respectively. Find maximum number of tuples in the output of natural join between tables $R1$ and $R2$ i.e. $R1 * R2$? ($*$- Natural Join) $30$ $20$ $50$ $1500$
Given two tables $R1(x,y)$ and $R2(y,z)$ with $50$ and $30$ number of tuples respectively. Find maximum number of tuples in the output of natural join between tables $R1$...
1.7k
views
answered
Dec 26, 2019
Others
ugcnetcse-dec2019-paper2
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–
2
answers
10
LSP Packets
Which of the following is true about link state routing ? A) LSP Packets contains information of the network. B) LSP Packets are forwarded using flooding algorithm. C) Routers in the network converted into tree before forwarding LSP Packet. D) All ... but partially according to me as each LSP packet contains distances only not all network information such as topology etc. explain pls.
Which of the following is true about link state routing ?A) LSP Packets contains information of the network.B) LSP Packets are forwarded using flooding algorithm.C) Route...
2.9k
views
answer edited
Nov 30, 2019
Computer Networks
computer-networks
link-state-routing
+
–
10
answers
11
GATE CSE 2014 Set 3 | Question: 28
An $IP$ router with a $\text{Maximum Transmission Unit (MTU)}$ of $1500$ bytes has received an $IP$ packet of size $4404\text{ bytes}$ with an $IP$ header of length $20\text{ bytes}$. The values of the relevant fields in the header of the third $IP$ ... $1,$ Datagram Length$: 1500;$ Offset$: 370$ $\text{MF bit}$: $0,$ Datagram Length$: 1424;$ Offset$: 2960$
An $IP$ router with a $\text{Maximum Transmission Unit (MTU)}$ of $1500$ bytes has received an $IP$ packet of size $4404\text{ bytes}$ with an $IP$ header of length $20\t...
21.3k
views
commented
Nov 28, 2019
Computer Networks
gatecse-2014-set3
computer-networks
ip-packet
normal
+
–
2
answers
12
Computer Network
The following character encoding is used in a data link protocol: $A: 01000111$ $B: 11100011$ $FLAG: 01111110$ $ESC: 11100000$ Show the bit sequence transmitted (in binary) for the four-character frame A B ESC FLAG when each of the following framing methods is used: (a) Byte count. (b) Flag bytes with byte stuffing. (c) Starting and ending flag bytes with bit stuffing.
The following character encoding is used in a data link protocol:$A: 01000111$ $B: 11100011$ $FLAG: 01111110$ $ESC: 11100000$Show the bit sequence transmitted (in binary)...
6.4k
views
answered
Nov 25, 2019
Computer Networks
framming
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–
1
answer
13
Bit Stuffing
In a data link protocol, the following character encoding is used: A → 01000111 B → 11100011 FLAG → 01111110 ESC → 11100000 Assuming that byte stuffing is employed for the four character frame A B ESC FLAG, transmitter sends it ... 01111110 01000111 11100011 11100000 11100000 01111110 01111110 C. 01111110 01000111 11100011 11100000 11100000 11100000 01111110 01111110 D. None of these
In a data link protocol, the following character encoding is used:A → 01000111 B → 11100011 FLAG → 01111110 ESC → 11100000Assuming that byte stuffing is employed ...
3.1k
views
commented
Nov 25, 2019
Computer Networks
computer-networks
bit-stuffing
+
–
2
answers
14
UGC NET CSE | June 2013 | Part 3 | Question: 22
What is the baud rate of standard 10 Mbps Ethernet? 10 megabaud 20 megabaud 30 megabaud 40 megabaud
What is the baud rate of standard 10 Mbps Ethernet?10 megabaud20 megabaud30 megabaud40 megabaud
6.1k
views
commented
Nov 24, 2019
Computer Networks
ugcnetcse-june2013-paper3
computer-networks
ethernet
+
–
3
answers
15
Let a cluster of stations share 48 Kbps of pure Aloha channel. Every station outputs frames of length 1024 bits on an average of every 50 seconds. Then what is the maximum value of number of stations?
6.1k
views
answer edited
Nov 24, 2019
Computer Networks
pure-aloha
+
–
1
answer
16
GATE Overflow | Digital Logic | Test 1 | Question: 16
The output of a gated S-R flip-flop changes only if the: flip-flop is set control input data has changed flip-flop is reset input data has no change
The output of a gated S-R flip-flop changes only if the:flip-flop is setcontrol input data has changedflip-flop is resetinput data has no change
536
views
comment edited
Nov 22, 2019
Digital Logic
digital-logic
go-digital-logic-1
flip-flop
+
–
1
answer
17
GATE Overflow | Digital Logic | Test 1 | Question: 10
Total number of full and half-adders require to add 32 bit numbers is 16 half adders , 16 full adders 1 half-adders , 31 full-adders 32 half-adders, 0 full-adders 16 half-adders, 31 full-adders
Total number of full and half-adders require to add 32 bit numbers is16 half adders , 16 full adders1 half-adders , 31 full-adders32 half-adders, 0 full-adders16 half-add...
383
views
commented
Nov 22, 2019
Digital Logic
digital-logic
go-digital-logic-1
adder
+
–
3
answers
18
GATE Overflow | Digital Logic | Test 1 | Question: 9
Reduce this Boolean Expression to one literal $\bar W X( \bar Z +\bar YZ ) + X( W+\bar WYZ)$ $W$ $Z$ $X$ $Y$
Reduce this Boolean Expression to one literal$$\bar W X( \bar Z +\bar YZ ) + X( W+\bar WYZ)$$$W$$Z$$X$$Y$
408
views
answered
Nov 22, 2019
Digital Logic
digital-logic
go-digital-logic-1
boolean-algebra
+
–
4
answers
19
GATE CSE 1992 | Question: 02-ii
All digital circuits can be realized using only Ex-OR gates Multiplexers Half adders OR gates
All digital circuits can be realized using onlyEx-OR gatesMultiplexersHalf addersOR gates
10.5k
views
answered
Nov 21, 2019
Digital Logic
gate1992
normal
digital-logic
digital-circuits
multiple-selects
functional-completeness
combinational-circuit
+
–
2
answers
20
Test by Bikram | Compiler Design | Test 1 | Question: 30
Consider the following grammar: $S \rightarrow L = P \mid P$ $L \rightarrow ^*P \mid id$ $P \rightarrow L$ The above grammar is: Ambiguous SLR(1) LALR(1) None of the above
Consider the following grammar:$S \rightarrow L = P \mid P$$L \rightarrow ^*P \mid id$$P \rightarrow L$The above grammar is:AmbiguousSLR(1)LALR(1)None of the above
694
views
comment edited
Nov 18, 2019
Compiler Design
tbb-cd-1
compiler-design
grammar
+
–
2
answers
21
Test by Bikram | Compiler Design | Test 1 | Question: 25
Consider the following grammar: $S \rightarrow aMd \mid bNd \mid aNe \mid bMe$ $M \rightarrow c$ $N \rightarrow c$ The grammar above is: LR(1) but not LALR(1) LALR(1) but not SLR(1) SLR(1) but not LR(1) LALR(1)
Consider the following grammar:$S \rightarrow aMd \mid bNd \mid aNe \mid bMe$$M \rightarrow c$$N \rightarrow c$The grammar above is:LR(1) but not LALR(1)LALR(1) but no...
520
views
answered
Nov 18, 2019
Compiler Design
tbb-cd-1
compiler-design
grammar
+
–
1
answer
22
Test by Bikram | Compiler Design | Test 1 | Question: 20
The least number of temporary variables required to create a $3$ address code sequence for the statement $L= P + R$ is ________.
The least number of temporary variables required to create a $3$ address code sequence for the statement $L= P + R$ is ________.
798
views
commented
Nov 18, 2019
Compiler Design
tbb-cd-1
numerical-answers
compiler-design
intermediate-code
+
–
11
answers
23
GATE CSE 2004 | Question: 81
Let $G_1=(V,E_1)$ and $G_2 =(V,E_2)$ be connected graphs on the same vertex set $V$ with more than two vertices. If $G_1 \cap G_2= (V,E_1\cap E_2)$ is not a connected graph, then the graph $G_1\cup G_2=(V,E_1\cup E_2)$ cannot have a cut vertex must have a cycle must have a cut-edge (bridge) has chromatic number strictly greater than those of $G_1$ and $G_2$
Let $G_1=(V,E_1)$ and $G_2 =(V,E_2)$ be connected graphs on the same vertex set $V$ with more than two vertices. If $G_1 \cap G_2= (V,E_1\cap E_2)$ is not a connected gr...
11.8k
views
commented
Nov 16, 2019
Algorithms
gatecse-2004
algorithms
graph-algorithms
normal
+
–
1
answer
24
Ullman (Compiler Design) Edition 2 Exercise 6.1 Question 2 (Page No. 363)
Construct the DAG and identify the value numbers for the subexpressions of the following expressions, assuming $+$ associates from the left. $a+b+(a+b)$ $a+b+a+b$ $a+a+((a+a+a+(a+a+a+a))$
Construct the DAG and identify the value numbers for the subexpressions of the following expressions, assuming $+$ associates from the left.$a+b+(a+b)$$a+b+a+b$$a+a+((a+a...
4.8k
views
commented
Nov 15, 2019
Compiler Design
ullman
compiler-design
three-address-code
directed-acyclic-graph
descriptive
+
–
4
answers
25
GATE CSE 2012 | Question: 36
Consider the program given below, in a block-structured pseudo-language with lexical scoping and nesting of procedures permitted. Program main; Var ... Procedure A1; Var ... Call A2; End A1 Procedure A2; Var ... Procedure A21; Var ... Call ... The correct set of activation records along with their access links is given by:
Consider the program given below, in a block-structured pseudo-language with lexical scoping and nesting of procedures permitted.Program main; Var ... Procedure A1; Var ....
13.0k
views
commented
Nov 11, 2019
Compiler Design
gatecse-2012
compiler-design
runtime-environment
normal
+
–
2
answers
26
GATE CSE 1990 | Question: 11a
What does the following program output? program module (input, output); var a:array [1...5] of integer; i, j: integer; procedure unknown (var b: integer, var c: integer); var i:integer; begin for i := 1 to 5 do a[i] := i; b:= 0; c := 0 for i := 1 to 5 do write (a[i]); ... b := 5; c := 6; end; begin i:=1; j:=3; unknown (a[i], a[j]); for i:=1 to 5 do write (a[i]); end;
What does the following program output?program module (input, output); var a:array [1...5] of integer; i, j: integer; procedure unknown (var b: integer, var c: integer); ...
1.8k
views
commented
Nov 11, 2019
Compiler Design
gate1990
descriptive
compiler-design
runtime-environment
parameter-passing
+
–
2
answers
27
Zeal Test Series 2018: Compiler Design - Runtime Environments
The two basic operations that are often performed with the symbol table are: 1. Set and reset 2. Set and insert 3. Insert and lookup 4. Reset and lookup
The two basic operations that are often performed with the symbol table are:1.Set and reset 2.Set and insert 3. Insert and lookup 4.Reset and lookup
1.6k
views
answered
Nov 11, 2019
Compiler Design
compiler-design
runtime-environment
zeal
zeal2018
+
–
8
answers
28
GATE CSE 2006 | Question: 73
The $2^n$ vertices of a graph $G$ corresponds to all subsets of a set of size $n$, for $n \geq 6$. Two vertices of $G$ are adjacent if and only if the corresponding sets intersect in exactly two elements. The number of connected components in $G$ is: $n$ $n + 2$ $2^{\frac{n}{2}}$ $\frac{2^{n}}{n}$
The $2^n$ vertices of a graph $G$ corresponds to all subsets of a set of size $n$, for $n \geq 6$. Two vertices of $G$ are adjacent if and only if the corresponding set...
8.7k
views
answered
Oct 22, 2019
Graph Theory
gatecse-2006
graph-theory
normal
graph-connectivity
+
–
3
answers
29
TIFR CSE 2018 | Part B | Question: 8
In an undirected graph $G$ with $n$ vertices, vertex $1$ has degree $1$, while each vertex $2,\ldots,n-1$ has degree $10$ and the degree of vertex $n$ is unknown, Which of the following statement must be TRUE on the graph $G$? There is a path ... Vertex $n$ has degree $1$. The diameter of the graph is at most $\frac{n}{10}$ All of the above choices must be TRUE
In an undirected graph $G$ with $n$ vertices, vertex $1$ has degree $1$, while each vertex $2,\ldots,n-1$ has degree $10$ and the degree of vertex $n$ is unknown, Which o...
5.5k
views
commented
Oct 18, 2019
Graph Theory
tifr2018
graph-theory
degree-of-graph
+
–
1
answer
30
Where to scan the barcode given in GateOverflow book
1.0k
views
answered
Oct 3, 2019
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