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Recent activity by shankargadri
2
answers
1
NIELIT 2016 DEC Scientist B (CS) - Section B: 19
Communication between a computer and a keyboard involves ___________ transmission Simplex Half-Duplex Automatic Full-Duplex
Communication between a computer and a keyboard involves ___________ transmissionSimplexHalf-DuplexAutomaticFull-Duplex
974
views
commented
Apr 21, 2020
Computer Networks
nielit2016dec-scientistb-cs
computer-networks
+
–
3
answers
2
process synchronization
DOES STRICT ALTERNATION APPROACH SATISFY BOUNDED WAITING CONDITION?? INT TURN;(RANDOMLY ASSIGNED) ---P1---- WHILE(TURN !=0); CRITICAL SECTION... TURN=1; ---P2--- WHILE(TURN!=1); CRITICAL SECTION TURN=0; PS: Though this methods has strict ... a chance to another process to enter CS, hence progress violated. But what about bounded wait condition ?? It also fails right??
DOES STRICT ALTERNATION APPROACH SATISFY BOUNDED WAITING CONDITION??INT TURN;(RANDOMLY ASSIGNED) -P1 WHILE(TURN !=0);CRITICAL SECTION...TURN=1; -P2 -WHILE(TURN!=1);...
1.6k
views
commented
Dec 7, 2019
Operating System
process-synchronization
operating-system
+
–
1
answer
3
My doubt on TLB and page fault
First read this whole thing what I am writing below: Case 1: If we have to access unit address in memory using TLB and we assume that no page fault occurs then, EMAT=p( T+M )+( 1-p ) (T+M+M) T=TLB access time, M= ... if there page fault occurs then how does the last calculated EMAT here affects the first Estimated memory access time which we have calculated using TLB?
First read this whole thing what I am writing below:Case 1: If we have to access unit address in memory using TLB and we assume that no page fault occurs then,EMAT=p( T+M...
2.6k
views
comment edited
Aug 5, 2019
Operating System
operating-system
translation-lookaside-buffer
hit-ratio
page-fault
effective-memory-access
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–
0
answers
4
ME Test series
Suppose a switch is built using a computer workstation and that it can forward packets at a rate of 500,000 packets per second, regardless (within limits) of size. Assume the workstation uses direct memory access (DMA) to move data in and out of its main memory ... and that the I/O bus has a bandwidth of 1 Gbps. At what packet size would the bus bandwidth become the limiting factor?
Suppose a switch is built using a computer workstation and that it can forward packets at a rate of 500,000 packets per second, regardless (within limits) of size. Assume...
1.1k
views
commented
Jul 22, 2019
4
answers
5
ISRO2009-69
The 'command' used to change contents of one database using the contents of another database by linking them on a common key field? Replace Join Change Update
The 'command' used to change contents of one database using the contents of another database by linking them on a common key field?ReplaceJoinChangeUpdate
4.6k
views
commented
Jun 12, 2019
Databases
isro2009
databases
bad-question
+
–
3
answers
6
ISRO2014-38
How many lines of output does the following C code produce? #include<stdio.h> float i=2.0; float j=1.0; float sum = 0.0; main() { while (i/j > 0.001) { j+=j; sum=sum+(i/j); printf("%f\n", sum); } } 8 9 10 11
How many lines of output does the following C code produce?#include<stdio.h float i=2.0; float j=1.0; float sum = 0.0; main() { while (i/j 0.001) { j+=j; sum=sum+(i/j); ...
5.7k
views
commented
Jun 7, 2019
Programming in C
isro2014
programming-in-c
loop
output
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–
9
answers
7
GATE CSE 2015 Set 1 | Question: 54
Let G be a connected planar graph with 10 vertices. If the number of edges on each face is three, then the number of edges in G is_______________.
Let G be a connected planar graph with 10 vertices. If the number of edges on each face is three, then the number of edges in G is_______________.
24.6k
views
commented
Apr 22, 2019
Graph Theory
gatecse-2015-set1
graph-theory
graph-connectivity
normal
graph-planarity
numerical-answers
+
–
5
answers
8
GATE CSE 2015 Set 2 | Question: 55
Which one of the following well-formed formulae is a tautology? $\forall x \, \exists y \, R(x,y) \, \leftrightarrow \, \exists y \, \forall x \, R(x, y)$ ... $\forall x \, \forall y \, P(x,y) \, \rightarrow \, \forall x \, \forall y \, P(y, x)$
Which one of the following well-formed formulae is a tautology? $\forall x \, \exists y \, R(x,y) \, \leftrightarrow \, \exists y \, \forall x \, R(x, y)$$( \forall x \,...
20.9k
views
commented
Apr 19, 2019
Mathematical Logic
gatecse-2015-set2
mathematical-logic
normal
first-order-logic
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–
9
answers
9
GATE IT 2005 | Question: 36
Let $P(x)$ and $Q(x)$ ...
Let $P(x)$ and $Q(x)$ be arbitrary predicates. Which of the following statements is always TRUE?$\left(\left(\forall x \left(P\left(x\right) \vee Q\left(x\right)\right)\r...
14.8k
views
commented
Apr 19, 2019
Mathematical Logic
gateit-2005
mathematical-logic
first-order-logic
normal
+
–
9
answers
10
GATE CSE 2018 | Question: 14
Consider the following statements regarding the slow start phase of the TCP congestion control algorithm. Note that cwnd stands for the TCP congestion window and MSS window denotes the Maximum Segments Size: The cwnd increases by $2$ MSS on every successful acknowledgment The cwnd ... true Only $\text{(iv)}$ is true Only $\text{(i)}$ and $\text{(iv)}$ are true
Consider the following statements regarding the slow start phase of the TCP congestion control algorithm. Note that cwnd stands for the TCP congestion window and MSS wind...
23.3k
views
commented
Apr 17, 2019
Computer Networks
gatecse-2018
computer-networks
tcp
congestion-control
normal
1-mark
+
–
9
answers
11
GATE CSE 2012 | Question: 34, ISRO-DEC2017-32
An Internet Service Provider (ISP) has the following chunk of CIDR-based IP addresses available with it: $245.248.128.0/20$. The ISP wants to give half of this chunk of addresses to Organization $A$, and a quarter to Organization $B$, while retaining the remaining ... $245.248.136.0/24 \text{ and } 245.248.132.0/21$
An Internet Service Provider (ISP) has the following chunk of CIDR-based IP addresses available with it: $245.248.128.0/20$. The ISP wants to give half of this chunk of a...
30.2k
views
commented
Apr 16, 2019
Computer Networks
gatecse-2012
computer-networks
subnetting
normal
isrodec2017
+
–
7
answers
12
GATE CSE 2005 | Question: 19
Which one of the following is true for a CPU having a single interrupt request line and a single interrupt grant line? Neither vectored interrupt nor multiple interrupting devices are possible Vectored interrupts are not possible ... and multiple interrupting devices are both possible Vectored interrupts are possible but multiple interrupting devices are not possible
Which one of the following is true for a CPU having a single interrupt request line and a single interrupt grant line?Neither vectored interrupt nor multiple interrupting...
21.1k
views
commented
Apr 12, 2019
Operating System
gatecse-2005
operating-system
io-handling
normal
+
–
5
answers
13
GATE IT 2007 | Question: 7
Which of the following input sequences for a cross-coupled $R-S$ flip-flop realized with two $NAND$ gates may lead to an oscillation? $11, 00$ $01, 10$ $10, 01$ $00, 11$
Which of the following input sequences for a cross-coupled $R-S$ flip-flop realized with two $NAND$ gates may lead to an oscillation?$11, 00$$01, 10$$10, 01$$00, 11$
22.4k
views
commented
Apr 7, 2019
Digital Logic
gateit-2007
digital-logic
normal
flip-flop
+
–
5
answers
14
GATE CSE 1991 | Question: 5-c
Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation delay through each flip flop and each AND gate is $10\;\text{ns}$. Also, assume that the setup time for the $JK$ inputs of the flip flops is negligible.
Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation delay through each flip flop and each AND gate is $...
23.1k
views
commented
Apr 6, 2019
Digital Logic
gate1991
digital-logic
sequential-circuit
flip-flop
digital-counter
+
–
7
answers
15
GATE CSE 2004 | Question: 84
The recurrence equation $ T(1) = 1$ $T(n) = 2T(n-1) + n, n \geq 2$ evaluates to $2^{n+1} - n - 2$ $2^n - n$ $2^{n+1} - 2n - 2$ $2^n + n $
The recurrence equation$ T(1) = 1$$T(n) = 2T(n-1) + n, n \geq 2$evaluates to$2^{n+1} - n - 2$$2^n - n$$2^{n+1} - 2n - 2$$2^n + n $
17.5k
views
commented
Jan 17, 2019
Algorithms
gatecse-2004
algorithms
recurrence-relation
normal
+
–
8
answers
16
GATE IT 2007 | Question: 63
A group of $15$ routers is interconnected in a centralized complete binary tree with a router at each tree node. Router $i$ communicates with router $j$ by sending a message to the root of the tree. The root then sends the message back down to router $j$ ... mean number of hops per message, assuming all possible router pairs are equally likely is $3$ $4.26$ $4.53$ $5.26$
A group of $15$ routers is interconnected in a centralized complete binary tree with a router at each tree node. Router $i$ communicates with router $j$ by sending a mess...
18.9k
views
commented
Dec 30, 2018
Computer Networks
gateit-2007
computer-networks
routing
binary-tree
normal
+
–
10
answers
17
GATE IT 2004 | Question: 88
Suppose that the maximum transmit window size for a TCP connection is $12000$ $\text{bytes}$. Each packet consists of $2000$ $\text{bytes}$. At some point in time, the connection is in slow-start phase with a current transmit window of $4000$ $\text{bytes}$. ... transmit window? $4000$ $\text{bytes}$ $8000$ $\text{bytes}$ $10000$ $\text{bytes}$ $12000$ $\text{bytes}$
Suppose that the maximum transmit window size for a TCP connection is $12000$ $\text{bytes}$. Each packet consists of $2000$ $\text{bytes}$. At some point in time, the co...
23.9k
views
answer edited
Dec 29, 2018
Computer Networks
gateit-2004
computer-networks
sliding-window
normal
+
–
18
answers
18
GATE CSE 2009 | Question: 57, ISRO2016-75
Frames of $\text{1000 bits}$ are sent over a $10^6$ $\text{bps}$ duplex link between two hosts. The propagation time is $\text{25 ms}$. Frames are to be transmitted into this link to maximally pack them in transit (within the link). What is the ... ? Assume that no time gap needs to be given between transmission of two frames. $I=2$ $I=3$ $I=4$ $I=5$
Frames of $\text{1000 bits}$ are sent over a $10^6$ $\text{bps}$ duplex link between two hosts. The propagation time is $\text{25 ms}$. Frames are to be transmitted into ...
48.7k
views
answered
Dec 28, 2018
Computer Networks
gatecse-2009
computer-networks
sliding-window
normal
isro2016
+
–
5
answers
19
GATE IT 2007 | Question: 44, ISRO2015-34
A hard disk system has the following parameters : Number of tracks $= 500$ Number of sectors/track $= 100$ Number of bytes /sector $= 500$ Time taken by the head to move from one track to adjacent track $= 1 \ ms$ Rotation speed $= 600 \ rpm$. What is ... time taken for transferring $250$ bytes from the disk ? $300.5 \ ms$ $255.5 \ ms$ $255 \ ms$ $300 \ ms$
A hard disk system has the following parameters :Number of tracks $= 500$Number of sectors/track $= 100$Number of bytes /sector $= 500$Time taken by the head to move from...
22.9k
views
commented
Dec 25, 2018
Operating System
gateit-2007
operating-system
disk
normal
isro2015
+
–
3
answers
20
GATE CSE 2008 | Question: 37, ISRO2009-38
The use of multiple register windows with overlap causes a reduction in the number of memory accesses for: Function locals and parameters Register saves and restores Instruction fetches $\text{I}$ only $\text{II}$ only $\text{III}$ only $\text{I}, \text{II}$ and $\text{III}$
The use of multiple register windows with overlap causes a reduction in the number of memory accesses for:Function locals and parametersRegister saves and restoresInstruc...
19.3k
views
commented
Dec 24, 2018
CO and Architecture
gatecse-2008
co-and-architecture
normal
isro2009
runtime-environment
+
–
8
answers
21
GATE CSE 2016 Set 1 | Question: 32
The stage delays in a $4$-stage pipeline are $800, 500, 400$ and $300$ picoseconds. The first stage (with delay $800$ picoseconds) is replaced with a functionality equivalent design involving two stages with respective delays $600$ and $350$ picoseconds. The throughput increase of the pipeline is ___________ percent.
The stage delays in a $4$-stage pipeline are $800, 500, 400$ and $300$ picoseconds. The first stage (with delay $800$ picoseconds) is replaced with a functionality equiva...
25.7k
views
commented
Dec 20, 2018
CO and Architecture
gatecse-2016-set1
co-and-architecture
pipelining
normal
numerical-answers
+
–
5
answers
22
GATE IT 2007 | Question: 41
Following table indicates the latencies of operations between the instruction producing the result and instruction using the result. ... to execute the above code segment assuming each instruction takes one cycle to execute? $7$ $10$ $13$ $14$
Following table indicates the latencies of operations between the instruction producing the result and instruction using the result.$$\begin{array}{|l|l|c|} \hline \textb...
25.0k
views
commented
Dec 18, 2018
CO and Architecture
gateit-2007
co-and-architecture
machine-instruction
normal
+
–
6
answers
23
GATE IT 2007 | Question: 6, ISRO2011-25
A processor takes $12$ cycles to complete an instruction I. The corresponding pipelined processor uses $6$ stages with the execution times of $3, 2, 5, 4, 6$ and $2$ cycles respectively. What is the asymptotic speedup assuming that a very large number of instructions are to be executed? $1.83$ $2$ $3$ $6$
A processor takes $12$ cycles to complete an instruction I. The corresponding pipelined processor uses $6$ stages with the execution times of $3, 2, 5, 4, 6$ and $2$ cycl...
13.3k
views
commented
Dec 18, 2018
CO and Architecture
gateit-2007
co-and-architecture
pipelining
normal
isro2011
+
–
4
answers
24
GATE CSE 2004 | Question: 63
Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$ ... after executing the HALT instruction, the return address (in decimal) saved in the stack will be $1007$ $1020$ $1024$ $1028$
Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$ $$\begin{array}{|l|l|c|} \hline \text {Instruction} & \t...
29.1k
views
commented
Dec 17, 2018
CO and Architecture
gatecse-2004
co-and-architecture
machine-instruction
normal
+
–
6
answers
25
GATE CSE 2014 Set 2 | Question: 55
Consider the main memory system that consists of $8$ memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for $100$ nanoseconds (ns) by the data, address, and control signals. ... bus at any time. The maximum number of stores (of one word each) that can be initiated in $1$ millisecond is ________
Consider the main memory system that consists of $8$ memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied ...
26.9k
views
commented
Dec 16, 2018
Operating System
gatecse-2014-set2
operating-system
memory-management
numerical-answers
normal
+
–
5
answers
26
GATE CSE 2013 | Question: 20
In a $k$-way set associative cache, the cache is divided into $v$ sets, each of which consists of $k$ lines. The lines of a set are placed in sequence one after another. The lines in set $s$ are sequenced before the lines in set $(s+1)$. The main memory blocks are numbered 0 onwards. The ... $(j \text{ mod } k) * v \text{ to } (j \text{ mod } k) * v + (v-1) $
In a $k$-way set associative cache, the cache is divided into $v$ sets, each of which consists of $k$ lines. The lines of a set are placed in sequence one after another. ...
14.2k
views
commented
Dec 16, 2018
CO and Architecture
gatecse-2013
co-and-architecture
cache-memory
normal
+
–
7
answers
27
GATE IT 2005 | Question: 12
The numbers $1, 2, .\dots n$ are inserted in a binary search tree in some order. In the resulting tree, the right subtree of the root contains $p$ nodes. The first number to be inserted in the tree must be $p$ $p + 1$ $n - p$ $n - p + 1$
The numbers $1, 2, .\dots n$ are inserted in a binary search tree in some order. In the resulting tree, the right subtree of the root contains $p$ nodes. The first number...
13.5k
views
commented
Dec 7, 2018
DS
gateit-2005
data-structures
normal
binary-search-tree
+
–
8
answers
28
GATE CSE 2009 | Question: 55
Consider the following relational schema: $\text{Suppliers}(\underline{\text{sid:integer}},\text{ sname:string, city:string, street:string})$ $\text{Parts}(\underline{\text{pid:integer}}, \text{ pname:string, color:string})$ ... of all suppliers who have supplied only non-blue part. Find the names of all suppliers who have not supplied only blue parts.
Consider the following relational schema:$\text{Suppliers}(\underline{\text{sid:integer}},\text{ sname:string, city:string, street:string})$ $\text{Parts}(\underline{\tex...
38.5k
views
answered
Oct 26, 2018
Databases
gatecse-2009
databases
sql
normal
+
–
5
answers
29
GATE CSE 2006 | Question: 82
Consider the diagram shown below where a number of LANs are connected by (transparent) bridges. In order to avoid packets looping through circuits in the graph, the bridges organize themselves in a spanning tree. First, the root bridge is identified as the bridge with the least serial number. ... $\text{B1, B5, B2, B3, B4}$ $\text{B1, B3, B4, B5, B2}$
Consider the diagram shown below where a number of LANs are connected by (transparent) bridges. In order to avoid packets looping through circuits in the graph, the bridg...
23.0k
views
commented
Oct 4, 2018
Computer Networks
gatecse-2006
computer-networks
bridges
normal
+
–
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