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Recent activity by shivam001
5
answers
1
GATE CSE 2000 | Question: 2.10
The simultaneous equations on the Boolean variables $x, y, z$ and $w$, $x + y + z = 1 $ $xy = 0$ $xz + w = 1$ $xy + \bar{z}\bar{w} = 0$ have the following solution for $x, y, z$ and $w,$ respectively: $0 \ 1 \ 0 \ 0$ $1 \ 1 \ 0 \ 1$ $1 \ 0 \ 1 \ 1$ $1 \ 0 \ 0 \ 0$
The simultaneous equations on the Boolean variables $x, y, z$ and $w$,$x + y + z = 1 $$xy = 0$$xz + w = 1$$xy + \bar{z}\bar{w} = 0$have the following solution for $x, y, ...
7.2k
views
commented
Sep 29, 2020
Digital Logic
gatecse-2000
digital-logic
boolean-algebra
easy
+
–
10
answers
2
GATE CSE 2016 Set 2 | Question: 08
Let, $x_{1} ⊕ x_{2} ⊕ x_{3} ⊕ x_{4}= 0$ where $x_{1}, x_{2}, x_{3}, x_{4}$ are Boolean variables, and $⊕$ is the XOR operator. Which one of the following must always be TRUE? $x_{1}x_{2}x_{3}x_{4} = 0$ $x_{1}x_{3} + x_{2} = 0$ $\bar{x}_{1} ⊕ \bar{x}_{3} = \bar{x}_{2} ⊕ \bar{x}_{4}$ $x_{1} + x_{2} + x_{3} + x_{4} = 0$
Let, $x_{1} ⊕ x_{2} ⊕ x_{3} ⊕ x_{4}= 0$ where $x_{1}, x_{2}, x_{3}, x_{4}$ are Boolean variables, and $⊕$ is the XOR operator.Which one of the following must alwa...
13.6k
views
answered
Sep 29, 2020
Digital Logic
gatecse-2016-set2
digital-logic
boolean-algebra
normal
+
–
3
answers
3
GATE CSE 2017 Set 2 | Question: 34
Consider the binary code that consists of only four valid codewords as given below: $00000, 01011, 10101, 11110$ Let the minimum Hamming distance of the code $p$ and the maximum number of erroneous bits that can be corrected by the code be $q$. Then the values of $p$ and $q$ are $p=3$ and $q=1$ $p=3$ and $q=2$ $p=4$ and $q=1$ $p=4$ and $q=2$
Consider the binary code that consists of only four valid codewords as given below:$00000, 01011, 10101, 11110$Let the minimum Hamming distance of the code $p$ and the ma...
15.6k
views
answered
Sep 29, 2020
Computer Networks
gatecse-2017-set2
computer-networks
error-detection
+
–
3
answers
4
UGC NET CSE | Junet 2015 | Part 2 | Question: 7
Consider a full-adder with the following input values : $x=1, y=0$ and $C_i$(carry input)$=0$ $x=0, y=1$ and $C_i =1$ Compute the value of S(sum) and $C_o$ (carry output) for the above input values : $S=1, C_o=0$ and $S=0, C_o=1$ $S=0, C_o=0$ and $S=1, C_o=1$ $S=1, C_o=1$ and $S=0, C_o=0$ $S=0, C_o=1$ and $S=1, C_o=0$
Consider a full-adder with the following input values :$x=1, y=0$ and $C_i$(carry input)$=0$$x=0, y=1$ and $C_i =1$Compute the value of S(sum) and $C_o$ (carry output) fo...
2.9k
views
answered
Sep 21, 2020
Digital Logic
ugcnetcse-june2015-paper2
digital-logic
full-adder
+
–
5
answers
5
GATE CSE 2007 | Question: 72
Consider the following program segment. Here $\text{R1, R2}$ and $\text{R3}$ ... is word addressable. After the execution of this program, the content of memory location $2010$ is: $100$ $101$ $102$ $110$
Consider the following program segment. Here $\text{R1, R2}$ and $\text{R3}$ are the general purpose registers.$$\small \begin{array}{|c|l|l||c|} \hline & \text {Instruct...
9.5k
views
answer edited
Sep 21, 2020
CO and Architecture
gatecse-2007
co-and-architecture
machine-instruction
interrupts
normal
+
–
3
answers
6
ISRO2017-1
If $\text{A}$ is a skew symmetric matrix then $\text{A}^t$ is Diagonal matrix $\text{A}$ $0$ $-\text{A}$
If $\text{A}$ is a skew symmetric matrix then $\text{A}^t$ isDiagonal matrix $\text{A}$$0$$-\text{A}$
5.5k
views
answered
Sep 21, 2020
Linear Algebra
isro2017
linear-algebra
matrix
+
–
3
answers
7
ISRO2020-74
Following declaration of an array of struct, assumes size of byte, short, int and long are $1,2,3$ and $4$ respectively. Alignment rule stipulates that $n$ - byte field must be located at an address divisible by $n$, the fields in the struct are not rearranged, padding is used ... is located at an address divisble by $8$, what is the total size of $C$, in bytes? $150$ $160$ $200$ $240$
Following declaration of an array of struct, assumes size of byte, short, int and long are $1,2,3$ and $4$ respectively. Alignment rule stipulates that $n$ – byte field...
3.4k
views
answered
Sep 16, 2020
Programming in C
isro-2020
programming
normal
structure
+
–
4
answers
8
GATE CSE 2016 Set 2 | Question: 31
Consider a processor with $64$ registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and twelve-bit immediate value. Each ... program has $100$ instructions, the amount of memory (in bytes) consumed by the program text is _________.
Consider a processor with $64$ registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers...
21.1k
views
answer edited
Sep 16, 2020
CO and Architecture
gatecse-2016-set2
instruction-format
machine-instruction
co-and-architecture
normal
numerical-answers
+
–
2
answers
9
UGC NET CSE | July 2018 | Part 2 | Question: 53
In a multi-user operating system, 30 requests are made to use a particular resource per hour, on an average. The probability that no requests are made in 40 minutes, when arrival pattern is a poisson distribution, is ______ $e^{-15}$ $1-e^{-15}$ $1-e^{-20}$ $e^{-20}$
In a multi-user operating system, 30 requests are made to use a particular resource per hour, on an average. The probability that no requests are made in 40 minutes, when...
6.6k
views
answered
Sep 13, 2020
Operating System
ugcnetcse-july2018-paper2
operating-system
+
–
4
answers
10
UGC NET CSE | July 2018 | Part 2 | Question: 52
In a paged memory, the page hit ratio is 0.40. The time required to access a page in secondary memory is equal to 120 ns. The time required to access a page in primary memory is 15 ns. The average time required to access a page is ____ 105 68 75 78
In a paged memory, the page hit ratio is 0.40. The time required to access a page in secondary memory is equal to 120 ns. The time required to access a page in primary me...
2.7k
views
commented
Sep 13, 2020
Operating System
ugcnetcse-july2018-paper2
operating-system
paging
+
–
9
answers
11
GATE CSE 2004 | Question: 18, ISRO2007-31
In an $SR$ latch made by cross-coupling two NAND gates, if both $S$ and $R$ inputs are set to $0$, then it will result in $Q = 0, Q' = 1$ $Q = 1, Q' = 0$ $Q = 1, Q' = 1$ Indeterminate states
In an $SR$ latch made by cross-coupling two NAND gates, if both $S$ and $R$ inputs are set to $0$, then it will result in$Q = 0, Q' = 1$$Q = 1, Q' = 0$$Q = 1, Q' = 1$Inde...
22.3k
views
commented
Sep 12, 2020
Digital Logic
gatecse-2004
digital-logic
easy
isro2007
flip-flop
+
–
4
answers
12
GATE CSE 2019 | Question: 28
Consider three machines M, N, and P with IP addresses $100.10.5.2, \: 100.10.5.5$, and $100.10.5.6$ respectively. The subnet mask is set to $255.255.255.252$ for all the three machines. Which one of the following is true? M, N, and P ... subnet Only M and N belong to the same subnet Only N and P belong to the same subnet M, N, and P belong to three different subnets
Consider three machines M, N, and P with IP addresses $100.10.5.2, \: 100.10.5.5$, and $100.10.5.6$ respectively. The subnet mask is set to $255.255.255.252$ for all the ...
9.3k
views
answer edited
Aug 21, 2020
Computer Networks
gatecse-2019
computer-networks
subnetting
2-marks
+
–
2
answers
13
GATE IT 2005 | Question: 71
A network with CSMA/CD protocol in the MAC layer is running at $1 \text{Gbps}$ over a $1 \text{km}$ cable with no repeaters. The signal speed in the cable is $2 \times 10^{8}\text{m/sec}$. The minimum frame size for this network should be: $10000 \text{bits}$ $10000 \text{bytes}$ $5000\text{ bits}$ $5000 \text{bytes}$
A network with CSMA/CD protocol in the MAC layer is running at $1 \text{Gbps}$ over a $1 \text{km}$ cable with no repeaters. The signal speed in the cable is $2 \times 1...
14.4k
views
commented
Aug 18, 2020
Computer Networks
gateit-2005
computer-networks
congestion-control
csma-cd
normal
+
–
3
answers
14
Kurose and Ross Edition 6 Exercise 3 Question R18 (Page No 288)
True or false? Consider congestion control in TCP. When the timer expires at the sender, the value of ssthresh is set to one half of its previous value.
True or false? Consider congestion control in TCP. When the timer expires at the sender, the value of ssthresh is set to one half of its previous value.
1.8k
views
answered
Aug 15, 2020
Computer Networks
computer-networks
kurose-and-ross
transport-layer
congestion-control
descriptive
tcp
+
–
9
answers
15
GATE CSE 1996 | Question: 2.1
Let $R$ denote the set of real numbers. Let $f:R\times R \rightarrow R \times R$ be a bijective function defined by $f(x,y) = (x+y, x-y)$. The inverse function of $f$ is given by $f^{-1} (x,y) = \left( \frac {1}{x+y}, \frac{1}{x-y}\right)$ ... $f^{-1}(x,y)=\left [ 2\left(x-y\right),2\left(x+y\right) \right ]$
Let $R$ denote the set of real numbers. Let $f:R\times R \rightarrow R \times R$ be a bijective function defined by $f(x,y) = (x+y, x-y)$. The inverse function of $f$ is ...
9.9k
views
answer edited
Aug 14, 2020
Set Theory & Algebra
gate1996
set-theory&algebra
functions
normal
+
–
2
answers
16
Expanding opcode technique
A CPU is designed to have 58 three-address instructions and 25 two-address instructions. The CPU is able to address a maximum of 16 memory locations. The length of machine code is the same for all instructions. If the list of the ... of twoaddress instructions iv) Determine the length of the machine code v) List the machine codes Detailed explanation would be helpful
A CPU is designed to have 58 three-address instructions and 25 two-address instructions. The CPU is able to address a maximum of 16 memory locations. The length of machin...
10.9k
views
commented
Aug 11, 2020
CO and Architecture
co-and-architecture
machine-instruction
+
–
9
answers
17
GATE CSE 2018 | Question: 47
Consider the following undirected graph $G$: Choose a value for $x$ that will maximize the number of minimum weight spanning trees (MWSTs) of $G$. The number of MWSTs of $G$ for this value of $x$ is ____.
Consider the following undirected graph $G$:Choose a value for $x$ that will maximize the number of minimum weight spanning trees (MWSTs) of $G$. The number of MWSTs of $...
17.7k
views
commented
Aug 6, 2020
Algorithms
gatecse-2018
algorithms
graph-algorithms
minimum-spanning-tree
numerical-answers
2-marks
+
–
4
answers
18
CN stop and wait bandwidth is 1.5 Mbps
If the bandwidth f the line is 1.5 Mbps, RTT is 45ms and packet size is 1KB, then find link utilization stop and wait protocol.
If the bandwidth f the line is 1.5 Mbps, RTT is 45ms and packet size is 1KB, then find link utilization stop and wait protocol.
11.2k
views
answered
Aug 5, 2020
Computer Networks
stop-and-wait
computer-networks
+
–
1
answer
19
Serializability and strict schedules
Answer is given as D. Not serializable, agreed. But how is it strict??
Answer is given as D. Not serializable, agreed. But how is it strict??
12.9k
views
commented
Jul 26, 2020
Databases
databases
serializability
strict-schedule
+
–
4
answers
20
GATE CSE 2015 Set 1 | Question: 27
Consider the following relation: ... P WHERE S.Roll_No= P.Roll_No GROUP BY S.STUDENT_Name The numbers of rows that will be returned by the SQL query is_________________.
Consider the following relation:$$\overset{\text{Student}}{\begin{array}{|c|c|}\hline\\\underline{\textbf{Roll_No}}& \textbf{Student_Name}\\\hline1& \text{Raj} \\...
17.3k
views
commented
Jul 17, 2020
Databases
gatecse-2015-set1
databases
sql
normal
numerical-answers
+
–
4
answers
21
GATE CSE 2005 | Question: 75
Let $E_1$ and $E_2$ be two entities in an $E/R$ diagram with simple-valued attributes. $R_1$ and $R_2$ are two relationships between $E_1$ and $E_2$, where $R_1$ is one-to-many and $R_2$ is many-to-many. $R_1$ and $R_2$ do not have ... of their own. What is the minimum number of tables required to represent this situation in the relational model? $2$ $3$ $4$ $5$
Let $E_1$ and $E_2$ be two entities in an $E/R$ diagram with simple-valued attributes. $R_1$ and $R_2$ are two relationships between $E_1$ and $E_2$, where $R_1$ is one-t...
18.6k
views
answered
Jul 15, 2020
Databases
gatecse-2005
databases
er-diagram
normal
+
–
5
answers
22
GATE CSE 2001 | Question: 2.2
Consider the following statements: $S_1:$ There exists infinite sets $A$, $B$, $C$ such that $A \cap (B \cup C)$ is finite. $S_2:$ There exists two irrational numbers $x$ and y such that $(x+y)$ ... $S_2$? Only $S_1$ is correct Only $S_2$ is correct Both $S_1$ and $S_2$ are correct None of $S_1$ and $S_2$ is correct
Consider the following statements:$S_1:$ There exists infinite sets $A$, $B$, $C$ such that $A \cap (B \cup C)$ is finite.$S_2:$ There exists two irrational numbers $x$ a...
9.0k
views
answered
Jun 28, 2020
Set Theory & Algebra
gatecse-2001
set-theory&algebra
normal
set-theory
+
–
4
answers
23
GATE CSE 1993 | Question: 17
Out of a group of $21$ persons, $9$ eat vegetables, $10$ eat fish and $7$ eat eggs. $5$ persons eat all three. How many persons eat at least two out of the three dishes?
Out of a group of $21$ persons, $9$ eat vegetables, $10$ eat fish and $7$ eat eggs. $5$ persons eat all three. How many persons eat at least two out of the three dishes?
8.2k
views
comment edited
Jun 28, 2020
Set Theory & Algebra
gate1993
set-theory&algebra
easy
set-theory
descriptive
+
–
4
answers
24
GATE CSE 2011 | Question: 20, UGCNET-June2013-II: 48
Let the page fault service time be $10$ milliseconds(ms) in a computer with average memory access time being $20$ nanoseconds (ns). If one page fault is generated every $10^6$ memory accesses, what is the effective access time for memory? $21$ ns $30$ ns $23$ ns $35$ ns
Let the page fault service time be $10$ milliseconds(ms) in a computer with average memory access time being $20$ nanoseconds (ns). If one page fault is generated every $...
26.8k
views
commented
Jun 9, 2020
Operating System
gatecse-2011
operating-system
virtual-memory
normal
ugcnetcse-june2013-paper2
+
–
1
answer
25
GATE2010 MN: GA-8
Consider the set of integers $\{1,2,3,\ldots,5000\}.$ The number of integers that is divisible by neither $3$ nor $4$ is $:$ $1668$ $2084$ $2500$ $2916$
Consider the set of integers $\{1,2,3,\ldots,5000\}.$ The number of integers that is divisible by neither $3$ nor $4$ is $:$$1668$$2084$$2500$$2916$
2.1k
views
commented
Jun 4, 2020
Quantitative Aptitude
general-aptitude
quantitative-aptitude
gate2010-mn
factors
+
–
2
answers
26
How many 256 X 4 RAM chips are needed to organize a memory of capacity of 32KB?
20.5k
views
commented
May 31, 2020
CO and Architecture
co-and-architecture
memory-interfacing
ram
+
–
4
answers
27
GATE CSE 1999 | Question: 2.22
The main difference(s) between a CISC and a RISC processor is/are that a RISC processor typically has fewer instructions has fewer addressing modes has more registers is easier to implement using hard-wired logic
The main difference(s) between a CISC and a RISC processor is/are that a RISC processor typicallyhas fewer instructionshas fewer addressing modeshas more registersis easi...
9.1k
views
commented
May 21, 2020
CO and Architecture
gate1999
co-and-architecture
normal
cisc-risc-architecture
multiple-selects
+
–
8
answers
28
TIFR CSE 2010 | Part A | Question: 2
The hour hand and the minute hands of a clock meet at noon and again at mid-night. In between they meet $N$ times, where $N$ is.: $6$ $11$ $12$ $13$ None of the above
The hour hand and the minute hands of a clock meet at noon and again at mid-night. In between they meet $N$ times, where $N$ is.:$6$$11$$12$$13$None of the above
2.4k
views
answered
May 21, 2020
Quantitative Aptitude
tifr2010
quantitative-aptitude
clock-time
+
–
6
answers
29
GATE CSE 1987 | Question: 1-V
The most relevant addressing mode to write position-independent codes is: Direct mode Indirect mode Relative mode Indexed mode
The most relevant addressing mode to write position-independent codes is:Direct modeIndirect modeRelative modeIndexed mode
15.2k
views
answered
May 21, 2020
CO and Architecture
gate1987
co-and-architecture
addressing-modes
easy
+
–
4
answers
30
GATE CSE 1998 | Question: 1.19
Which of the following addressing modes permits relocation without any change whatsoever in the code? Indirect addressing Indexed addressing Base register addressing PC relative addressing
Which of the following addressing modes permits relocation without any change whatsoever in the code?Indirect addressingIndexed addressingBase register addressingPC relat...
11.0k
views
commented
May 21, 2020
CO and Architecture
gate1998
co-and-architecture
addressing-modes
easy
+
–
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