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Recent activity by someshawasthi
1
answer
1
self doubt
while solving question of work and time when should I use : 1day concept or lcm concept or man work time formula please answer
while solving question of work and time when should I use : 1day concept or lcm concept or man work time formulaplease answer
271
views
asked
Apr 26, 2023
Quantitative Aptitude
self-doubt
+
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0
answers
2
discrete mathematics
The maximum number of edges possible in a graph G with 9 vertices which is 3 colourable is equal to A 24 B 27 C 36 D None of the above
The maximum number of edges possible in a graph G with 9 vertices which is 3 colourable is equal toA 24B 27C 36D None of the above
503
views
asked
Mar 27, 2023
Graph Theory
graph-theory
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0
answers
3
digital
Which of these boolean functions is/are functionally complete? A f(x, y, z) = x' + yz' B f(x, y) = x' + xy C f(x, y, z) = xy' + x' + x'z D None of these
Which of these boolean functions is/are functionally complete?A f(x, y, z) = x' + yz'B f(x, y) = x' + xyC f(x, y, z) = xy' + x' + x'zD None of th...
252
views
asked
Mar 27, 2023
Digital Logic
digital-logic
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0
answers
4
doubt
where can I find all barc’s PYQ
where can I find all barc’s PYQ
258
views
asked
Mar 14, 2023
BARC
self-doubt
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1
answer
5
self doubt
is there any output difference between active high decoder and active low decoder
is there any output difference between active high decoder and active low decoder
160
views
asked
Mar 5, 2023
Digital Logic
self-doubt
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–
2
answers
6
ripple carry adder
Half Adder is implemented with XOR and AND gate. A. FA is implemented with 2 HA and 1 OR gate The propagation delay of XOR -gate is twice that of AND / OR gate. Propagation delay of AND/OR is 1.2 ms. A 4-bit ripple carry binary adder is implemented using 4 full adder. the total propagation time of this 4 bit binary adder in micro second is ________?
Half Adder is implemented with XOR and AND gate. A. FA is implemented with 2 HA and 1 OR gate The propagation delay of XOR -gate is twice that of AND / OR gate. Propagati...
1.9k
views
asked
Mar 4, 2023
Digital Logic
digital-logic
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–
1
answer
7
set theory
If A = {1, 2, 3, . . . . . . 10} then the number of 4 element subsets of A containing ‘2’?
If A = {1, 2, 3, . . . . . . 10} then the number of 4 element subsets of A containing ‘2’?
374
views
asked
Feb 27, 2023
Set Theory & Algebra
set-theory
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–
1
answer
8
binary search tree
Consider a binary search tree, while searching the key value 4, key values 1, 2, 3, 6, 8, 9, 10 and 11 are traversed not necessarily in the order given. How many different orders are possible in which these key values can occur on the search path from the root to the node containing value 4?
Consider a binary search tree, while searching the key value 4, key values 1, 2, 3, 6, 8, 9, 10 and 11 are traversed not necessarily in the order given. How many differen...
472
views
asked
Feb 27, 2023
DS
data-structures
binary-search-tree
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1
answer
9
self doubt
true/ false cpu generate logical address(which is for Rom/secondary memory) and MAR stores physical address which is (data/instruction ready for execution in ram)
true/ falsecpu generate logical address(which is for Rom/secondary memory) and MAR stores physical address which is (data/instruction ready for execution in ram)
340
views
asked
Feb 20, 2023
CO and Architecture
co-and-architecture
logical-reasoning
true-false
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0
answers
10
ripple counter
In a 4-bit binary ripple counter, for every input clock pulse (a) All the flip-flops get clocked simultaneously. (b) Only one flip-flop get clocked at a time. (c) Two of the flip-flops get clocked at a time. (d) All the above statements are false.
In a 4-bit binary ripple counter, for every input clock pulse(a) All the flip-flops get clocked simultaneously.(b) Only one flip-flop get clocked at a time.(c) Two of the...
318
views
commented
Jan 18, 2023
Digital Logic
digital-counter
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0
answers
11
self doubt
if i have given 2 flip flop clock simultaneously and 2 flip flop clock non simultaneously what is it synchronous counter or asynchronous counter ? why?
if i have given 2 flip flop clock simultaneously and 2 flip flop clock non simultaneously what is it synchronous counter or asynchronous counter ? why?
281
views
asked
Jan 18, 2023
Digital Logic
digital-counter
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0
answers
12
toc
is it a regular language? why?
is it a regular language? why?
357
views
commented
Jan 17, 2023
Theory of Computation
theory-of-computation
regular-language
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0
answers
13
set, relation
Consider the partition of a set having 3 block of 5 elements each, 4 block of 2 elements each and 2 block of 3 elements in each block. Find the cardinality of equivalence relation.
Consider the partition of a set having 3 block of 5 elements each, 4 block of 2 elements each and 2 block of 3 elements in each block.Find the cardinality of equivalence ...
465
views
commented
Jan 17, 2023
Set Theory & Algebra
discrete-mathematics
set-theory
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0
answers
14
SQL
consider following relation How many number of records resulted by following SQL query? Select $T_{1}.A$ From R Where Exists (Select Count (*) From S Where R .C<S.F and S. E > 10 ); A 3 B 2 C 1 D 0
consider following relation How many number of records resulted by following SQL query?Select $T_{1}.A$From RWhere Exists (Select Count (*) From S Where R .C<S.F and S....
279
views
edited
Jan 17, 2023
Databases
made-easy-test-series
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2
answers
15
limits
the value of $lim_{x-> 0}(1-sinx.cosx)^{cosec2x}$ is: A $e^{2}$ B $e^{-2}$ C$e^{1/2}$ D $e^{-1/2}$
the value of $lim_{x- 0}(1-sinx.cosx)^{cosec2x}$ is:A $e^{2}$B $e^{-2}$C$e^{1/2}$D $e^{-1/2}$
393
views
commented
Jan 16, 2023
Calculus
limits
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0
answers
16
network layer
Which of following is false in case of ICMP protocol? and why? A Parameter problem message is transmitted by ICMP, when a router is congested.. B When noise has modified some IP header bits, then calculated IP header checksum will not be equal to received ... quench message will be transmitted C No ICMP error message will be transmitted for the loop back address packet, if it is lost.
Which of following is false in case of ICMP protocol? and why?A Parameter problem message is transmitted by ICMP, when a router is congested..B When noise has modified so...
510
views
asked
Jan 7, 2023
Computer Networks
computer-networks
network-layer
icmp
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2
answers
17
Self doubt
Does bandwidth gets divided in tdma? How does bandwidth gets affected in fdma, tdma, cdma
Does bandwidth gets divided in tdma?How does bandwidth gets affected in fdma, tdma, cdma
450
views
asked
Jan 7, 2023
Computer Networks
computer-networks
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1
answer
18
number system
The decimal equivalent value of given 2's complement number 101001.10 is A -20.5 B -23.5 C -22.5
The decimal equivalent value of given 2's complement number 101001.10 is A -20.5B -23.5C -22.5
255
views
asked
Jan 4, 2023
Digital Logic
number-system
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2
answers
19
storage class
find the output of following program main() { extern int a; a=5; printf("%d",a); }
find the output of following programmain(){ extern int a; a=5; printf("%d",a);}
749
views
commented
Nov 30, 2022
Programming in C
storage-classes-in-c
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1
answer
20
Quicksort
In Quick sort of the following numbers, if the pivot is chosen as the first element, what will be the order of the numbers after the use of partition function ? Assume we are sorting in increasing order. 11, 15, 9, 13, 17, 7, 5, 12, 6, 18
In Quick sort of the following numbers, if the pivot is chosen as the first element, what will be the order of the numbers after the use of partition function ? Assume we...
600
views
asked
Nov 25, 2022
Algorithms
quick-sort
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0
answers
21
cache memory
Consider a process where each instruction takes on average 3 cycle and there are 1.8 references to memory per instruction. A program with 50000 instruction is executed on this machine using a split cache of 32KB, obtained a 85% bit rate, 3ns bit time and 21ns miss penalty the execution time for the cache is ___ (μsec)
Consider a process where each instruction takes on average 3 cycle and there are 1.8 references to memory per instruction. A program with 50000 instruction is executed on...
296
views
commented
Nov 17, 2022
CO and Architecture
co-and-architecture
cache-memory
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1
answer
22
cache memory
Consider a RISC processor with an ideal CPI, where 25% of the total instructions are LOAD and STORE instruction. Time to accessing main memory is 100 clock cycles and accessing of the cache memory required 2 clock cycles. If cache miss rate is 2%, then the effective CPI for the system with the cache is ____.
Consider a RISC processor with an ideal CPI, where 25% of the total instructions are LOAD and STORE instruction. Time to accessing main memory is 100 clock cycles and acc...
368
views
asked
Nov 17, 2022
CO and Architecture
cache-memory
clock-cycles
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–
1
answer
23
instruction-format
Assume an instruction set that uses a fixed 31 bit instruction length. Operand specifies are 4 bits in length. If there are m-three operand instructions in total, then how many two instructions are possible at maximum?
Assume an instruction set that uses a fixed 31 bit instruction length. Operand specifies are 4 bits in length. If there are m-three operand instructions in total, then ho...
536
views
commented
Oct 28, 2022
CO and Architecture
co-and-architecture
instruction-format
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1
answer
24
control signal
28 control signal to each micro operation has 2 control signal active at a time. Find minimum no. of bits need for control field.
28 control signal to each micro operation has 2 control signal active at a time. Find minimum no. of bits need for control field.
238
views
asked
Oct 27, 2022
CO and Architecture
co-and-architecture
control-unit
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1
answer
25
SelfDoubt
During the instruction fetch does the program counter increment in the same clock cycle or it take next clock cycle
During the instruction fetch does the program counter increment in the same clock cycle or it take next clock cycle
354
views
asked
Oct 27, 2022
CO and Architecture
co-and-architecture
self-doubt
machine-instruction
clock-cycles
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