Find the recurrence relation satisfied by $R_{n},$ where $R_{n}$ is the number of regions that a plane is divided into by $n$ lines, if no two of the lines are parallel and no three of the lines go through the same point. Find $R_{n}$ using iteration.
Find a recurrence relation for the number of bit strings of length $n$ that contain the string $01.$ I am getting a recurrence like An = 2^(n-2) + 2A(n-1) - A (N-2) .Answer is not given for this question.Please help and explain your steps.
Consider the following sequence of instructions executed on the five-stage pipelined processor: LW $1, 30($6) ADD $2,$4, $2 ADD$1, $3,$5 SW $2, 20($4) ADD $1,$1, $4 Assuming there is no forwarding, calculate the number of clock cycles needed to execute above program ? 1 vote 4 Consider a$5$...$\text{(in ns)}$needed to execute the program. 0 votes 5 What is output Y? 0 votes 6 0 votes 7 A sequential circuit with two$D$flip-flops$A$and$B$, two inputs$x$and$y$, and one output$z$is specified by the following next-state and output equations :$A(t+1)= x'y + xBB(t+1)= x'A + xBz = A$(a) Draw the logic diagram of the circuit. (b) List the state table for the sequential circuit. (c) Draw the corresponding state diagram. 0 votes 8 How many rounds are in the elimination tournament described in question$14$when there are$32$teams? 0 votes 9 Suppose that there are$n = 2^{k}$teams in an elimination tournament, where there are$\frac{n}{2}$games in the first round, with the$\frac{n}{2} = 2^{k-1}$winners playing in the second round, and so on. Develop a recurrence relation for the number of rounds in the tournament. 0 votes 10 Given explanation. I am not able to understand what is asked in the question. Please explain. 0 votes 11 I am getting (C). But answer given is (B). Where I have gone wrong? 0 votes 12 0 votes 13 The number of AND gates are present inside a 5-bit carry look ahead generator circuit are ______. 0 votes 14 Given explanation: I always fail to solve such questions. Please tell what is the approach to solve such problems? 0 votes 15 Consider a disk drive with 16 surfaces, 512 tracks / surface, 256 sectors / track, 8 KB / sector with a rotation speed of 3600 rpm. The disk is operated in cycle stealing mode where by whenever 1 B word is ready it is sent to memory, similarly. For writing ... cycle. The time for each memory cycle is 50 nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is ______ 1 vote 16 A CPU has five-stage pipeline and runs at 1 GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching ... If each instruction takes one cycle to complete on average, then total execution time of the program is i am getting 1.32 1 vote 17 Consider two instruction sequences: a. SW R16,-100(R6) LW R4, 8(R16) ADD R5,R4,R4 b. OR R1,R2,R3 OR R2,R1,R3 OR R1,R1,R2 Add NOP instructions to this code to eliminate hazards if there is ALU-ALU forwarding only (no forwarding from the MEM to the EX stage). 1 vote 18 anyone elaborate the reason for each stall cycles. 0 votes 19 A$5-$stage pipelined processor has IF,ID,EX,MEM and WB . WB stage operation is divided into two parts. In the first part register write operation and in second part register read operation is performed. The latency of those stages are$300,400,500,500,300$(in nano seconds) respectively.Consider ...$I_{4}$SUB$R_{1},R_{7},R_{4}R_{1} <- R_{7} - R_{4}$The program execution time__________ns? 0 votes 20 Consider the following specifications: Hit ratio for read = 0.8, Hit ratio for write = 0.9 Block size =2 words, cache of 10 ns is 10 times faster than main memory On any miss entire block is moved from main memory to cache memory 20% references are for write operations What is avg access time with write through using 1) Write allocate 2) No write allocate 0 votes 21 my doubt 1) default is hierarchal or simultaneous. 2)will we use hierarchical or simultaneous here..also explain. 0 votes 22 Array A contains$256$elements of$4$bytes each. Its first element is stored at physical address$4,096.$Array B contains$512$elements of$4$bytes each. Its first element is stored at physical address$8,192.$Assume that only arrays A and B can be cached in an initially empty, ... bytes will be written to memory if the cache has a write-through policy?$a) 0b) 256c) 1,024d) 2,048$0 votes 23 For a floating point representation with 64 bits in the mantissa and$12$bits in the unbiased exponent, the number of significant digits in decimal and the maximum (positive) value of the exponent in decimal will be _______________________ 0 votes 24 After executing one CALL instruction, the content of PC is decremented by$8$( for storing PC and flag register content on stack memory) Consider the following Memory address Instruction$2502$: MOV A,$562503$:ADD A,B$2504$:CALL$85002506$:DCR B ... PC and flag register. Let content of SP be$6950$when PC content is$2503$content of SP when PC reaches$2508$is ____________________ 0 votes 25 A 32 bit machine processor has 32 register, each of which is 16 bit long. each instruction is specified with four field, namely operation part, immediate operand in addition to two register operands. assume that the immediate operand is signed integer in signed 2' ... that can be represented in immediate operand field is +4095. max number of instruction that can be permitted by this processor is.? 0 votes 26 Consider the following statements$S_{1}:$The set of string described by a rule is called pattern associated with the token.$S_{2}:$A lexeme is a sequence of character in the source program that is matched by Pattern for a token. Which of the following statement is/are true? Both$S_{1}$...$S_{2}$is false$S_{2}$is true$S_{1}$is false Both$S_{1}$and$S_{2}$are false 0 votes 27 Suppose that in$500$memory references there are$50$misses in the first level cache and$20$misses in second level cache. Assume miss penalty from the$L_{2}$cache to memory is$100$cycles. The hit time of$L_{2}$cache is$20$cycle. The hit time of$L_{1}$cache is$10$cycles. If there are$2.5$memory references per instruction. How many average stall cycle per instruction? 1 vote 28 Suppose that in 250 memory references there are 30 misses in first level cache and 10 misses in second level cache. Assume that miss penalty from L$_2$cache memory are 50 cycles. The hit time of L$_2$cache is 10 cycles. The hit time of the L$_1$cache is 5 ... 1250 number of cycles with given misses = 1800 stall cycles = 1800-1250 = 550 number of stalls/instruction= 550/200 = 2.75 please verify 0 votes 29 For parameters$a$and$b$, both of which are$\omega(1)$,$T(n) = T(n^{1/a})+1$, and$T(b)=1$. Then$T(n)$is$\Theta (\log_a \log _b n)\Theta (\log_{ab} n$)$\Theta (\log_{b} \log_{a} \: n$)$\Theta (\log_{2} \log_{2} n$) 3 votes 30 Consider the following C functions. int fun1(int n) { static int i= 0; if (n > 0) { ++i; fun1(n-1); } return (i); } int fun2(int n) { static int i= 0; if (n>0) { i = i+ fun1 (n) ; fun2(n-1) ; } return (i); } The return value of$\text{fun}2 (5)\$ is _________