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Answers by srestha
0
votes
1
Kenneth Rosen Edition 7 Exercise 8.1 Question 21 (Page No. 511)
Find the recurrence relation satisfied by $R_{n},$ where $R_{n}$ is the number of regions that a plane is divided into by $n$ lines, if no two of the lines are parallel and no three of the lines go through the same point. Find $R_{n}$ using iteration.
Find the recurrence relation satisfied by $R_{n},$ where $R_{n}$ is the number of regions that a plane is divided into by $n$ lines, if no two of the lines are parallel a...
1.1k
views
answered
Jul 11, 2020
Combinatory
kenneth-rosen
discrete-mathematics
counting
descriptive
+
–
0
votes
2
Rosen-Advance Counting Technique-26
Find a recurrence relation for the number of bit strings of length $n$ that contain the string $01.$ I am getting a recurrence like An = 2^(n-2) + 2A(n-1) - A (N-2) .Answer is not given for this question.Please help and explain your steps.
Find a recurrence relation for the number of bit strings of length $n$ that contain the string $01.$I am getting a recurrence like An = 2^(n-2) + 2A(n-1) - A (N-2) .Answe...
547
views
answered
Jul 11, 2020
Combinatory
kenneth-rosen
+
–
0
votes
3
PIPELINING
Consider the following sequence of instructions executed on the five-stage pipelined processor: LW $1, 30($6) ADD $2, $4, $2 ADD $1, $3, $5 SW $2, 20($4) ADD $1, $1, $4 Assuming there is no forwarding, calculate the number of clock cycles needed to execute above program ?
Consider the following sequence of instructions executed on the five-stage pipelined processor:LW $1, 30($6)ADD $2, $4, $2ADD $1, $3, $5SW $2, 20($4)ADD $1, $1, $...
773
views
answered
Jun 4, 2020
CO and Architecture
pipelining
computer-organisation
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–
1
votes
4
ISI2018-PCB-CS8
Consider a $5$ ... $\text{(in ns)}$ needed to execute the program.
Consider a $5$-stage instruction pipeline. The stages and the corresponding stage delays are given below.$$\begin{array}{|l|l|}\hline \textbf{Instruction}&\textbf{Stage d...
1.3k
views
answered
Jun 4, 2020
Operating System
isi2018-pcb-cs
co-and-architecture
pipelining
descriptive
+
–
0
votes
5
sequential circuit
What is output Y?
What is output Y?
299
views
answered
May 19, 2020
0
votes
6
Synchronous Counter
1.1k
views
answered
May 19, 2020
Digital Logic
digital-logic
synchronous-asynchronous-circuits
digital-counter
+
–
2
votes
7
Digital Logic Morris Mono 5.6
A sequential circuit with two $D$ flip-flops $A$ and $B$, two inputs $x$ and $y$, and one output $z$ is specified by the following next-state and output equations : $A(t+1)= x'y + xB$ $B(t+1)= x'A + xB$ $z = A$ (a) Draw the logic diagram of the circuit. (b) List the state table for the sequential circuit. (c) Draw the corresponding state diagram.
A sequential circuit with two $D$ flip-flops $A$ and $B$, two inputs $x$ and $y$, and one output $z$ is specified by the following next-state and output equations : ...
2.5k
views
answered
May 16, 2020
Digital Logic
digital-logic
sequential
reference-book
+
–
0
votes
8
Kenneth Rosen Edition 7 Exercise 8.3 Question 15 (Page No. 535)
How many rounds are in the elimination tournament described in question $14$ when there are $32$ teams?
How many rounds are in the elimination tournament described in question $14$ when there are $32$ teams?
524
views
answered
May 15, 2020
Combinatory
kenneth-rosen
discrete-mathematics
counting
recurrence-relation
descriptive
+
–
0
votes
9
Kenneth Rosen Edition 7 Exercise 8.3 Question 14 (Page No. 535)
Suppose that there are $n = 2^{k}$ teams in an elimination tournament, where there are $\frac{n}{2}$ games in the first round, with the $\frac{n}{2} = 2^{k-1}$ winners playing in the second round, and so on. Develop a recurrence relation for the number of rounds in the tournament.
Suppose that there are $n = 2^{k}$ teams in an elimination tournament, where there are $\frac{n}{2}$ games in the first round, with the $\frac{n}{2} = 2^{k-1}$ winners pl...
1.8k
views
answered
May 15, 2020
Combinatory
kenneth-rosen
discrete-mathematics
counting
recurrence-relation
descriptive
+
–
0
votes
10
Question on K-maps
Given explanation. I am not able to understand what is asked in the question. Please explain.
Given explanation.I am not able to understand what is asked in the question. Please explain.
5.2k
views
answered
May 14, 2020
Digital Logic
digital-logic
k-map
+
–
1
votes
11
Ace Test Series: Digital Logic - ROM
I am getting (C). But answer given is (B). Where I have gone wrong?
I am getting (C). But answer given is (B). Where I have gone wrong?
2.0k
views
answered
May 14, 2020
CO and Architecture
ace-test-series
digital-logic
rom
+
–
0
votes
12
Number of Gate levels required
728
views
answered
May 14, 2020
Digital Logic
digital-logic
test-series
+
–
0
votes
13
MadeEasy Test Series: Digital Logic - Carry Generator
The number of AND gates are present inside a 5-bit carry look ahead generator circuit are ______.
The number of AND gates are present inside a 5-bit carry look ahead generator circuit are ______.
1.2k
views
answered
May 14, 2020
Digital Logic
digital-logic
carry-generator
made-easy-test-series
+
–
0
votes
14
Please explain how to approach such problems
Given explanation: I always fail to solve such questions. Please tell what is the approach to solve such problems?
Given explanation:I always fail to solve such questions. Please tell what is the approach to solve such problems?
431
views
answered
May 14, 2020
Digital Logic
digital-logic
+
–
0
votes
15
CPU blocked time in DMA
Consider a disk drive with 16 surfaces, 512 tracks / surface, 256 sectors / track, 8 KB / sector with a rotation speed of 3600 rpm. The disk is operated in cycle stealing mode where by whenever 1 B word is ready it is sent to memory, ... . The time for each memory cycle is 50 nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is ______
Consider a disk drive with 16 surfaces, 512 tracks / surface, 256 sectors / track, 8 KB / sector with a rotation speed of 3600 rpm. The disk is operated in cycle stealing...
636
views
answered
May 5, 2020
CO and Architecture
co-and-architecture
dma
+
–
1
votes
16
previousgatemodification
A CPU has five-stage pipeline and runs at 1 GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The ... each instruction takes one cycle to complete on average, then total execution time of the program is i am getting 1.32
A CPU has five-stage pipeline and runs at 1 GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the tar...
907
views
answered
Apr 30, 2020
1
votes
17
Dealing with ALU-ALU forwarding
Consider two instruction sequences: a. SW R16,-100(R6) LW R4, 8(R16) ADD R5,R4,R4 b. OR R1,R2,R3 OR R2,R1,R3 OR R1,R1,R2 Add NOP instructions to this code to eliminate hazards if there is ALU-ALU forwarding only (no forwarding from the MEM to the EX stage).
Consider two instruction sequences:a. SW R16,-100(R6) LW R4, 8(R16) ADD R5,R4,R4b. OR R1,R2,R3 OR R2,R1,R3 OR R1,R1,R2Add NOP instructions to this code to eli...
2.4k
views
answered
Apr 30, 2020
CO and Architecture
co-and-architecture
pipelining
operand-forwarding
+
–
1
votes
18
Stall Cycles-Without Forwarding
anyone elaborate the reason for each stall cycles.
anyone elaborate the reason for each stall cycles.
2.0k
views
answered
Apr 29, 2020
CO and Architecture
stall
cycle
+
–
0
votes
19
Pipeline (With split phase- With forwarding)
A $5-$ stage pipelined processor has IF,ID,EX,MEM and WB . WB stage operation is divided into two parts. In the first part register write operation and in second part register read operation is performed. The latency of those stages are $300,400,500,500,300$ ... SUB $R_{1},R_{7},R_{4}$ $R_{1} <- R_{7} - R_{4}$ The program execution time__________ns?
A $5-$ stage pipelined processor has IF,ID,EX,MEM and WB . WB stage operation is divided into two parts. In the first part register write operation and in second part reg...
1.4k
views
answered
Apr 27, 2020
CO and Architecture
co-and-architecture
operand-forwarding
+
–
0
votes
20
Doubt on Write through
Consider the following specifications: Hit ratio for read = 0.8, Hit ratio for write = 0.9 Block size =2 words, cache of 10 ns is 10 times faster than main memory On any miss entire block is moved from main memory to cache memory 20% references are for write operations What is avg access time with write through using 1) Write allocate 2) No write allocate
Consider the following specifications:Hit ratio for read = 0.8,Hit ratio for write = 0.9Block size =2 words,cache of 10 ns is 10 times faster than main memory On any miss...
985
views
answered
Apr 25, 2020
CO and Architecture
co-and-architecture
cache-memory
write-through
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–
0
votes
21
CO-Write Through
my doubt 1) default is hierarchal or simultaneous. 2)will we use hierarchical or simultaneous here..also explain.
my doubt1) default is hierarchal or simultaneous.2)will we use hierarchical or simultaneous here..also explain.
525
views
answered
Apr 24, 2020
CO and Architecture
co-and-architecture
+
–
0
votes
22
MadeEasy Test Series: CO & Architecture - Cache Memory
Array A contains $256$ elements of $4$ bytes each. Its first element is stored at physical address $4,096.$ Array B contains $512$ elements of $4$ bytes each. Its first element is stored at physical address $8,192.$ Assume that only arrays A and B can ... to memory if the cache has a write-through policy? $a) 0$ $b) 256$ $c) 1,024$ $d) 2,048$
Array A contains $256$ elements of $4$ bytes each. Its first element is stored at physical address $4,096.$ Array B contains $512$ elements of $4$ bytes each. Its first e...
2.7k
views
answered
Apr 23, 2020
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
+
–
2
votes
23
#Number System
For a floating point representation with 64 bits in the mantissa and $12$ bits in the unbiased exponent, the number of significant digits in decimal and the maximum (positive) value of the exponent in decimal will be _______________________
For a floating point representation with 64 bits in the mantissa and $12$ bits in the unbiased exponent, the number of significant digits in decimal and the maximum (posi...
637
views
answered
Apr 21, 2020
CO and Architecture
floating-point-representation
co-and-architecture
+
–
0
votes
24
Computer Organisation
After executing one CALL instruction, the content of PC is decremented by $8$ ( for storing PC and flag register content on stack memory) Consider the following Memory address Instruction $2502$ : MOV A,$56$ $2503$ :ADD A,B $2504$ :CALL $8500$ ... flag register. Let content of SP be $6950$ when PC content is $2503$ content of SP when PC reaches $2508$ is ____________________
After executing one CALL instruction, the content of PC is decremented by $8$ ( for storing PC and flag register content on stack memory)Consider the followingMemory addr...
704
views
answered
Apr 20, 2020
CO and Architecture
call-instruction
co-and-architecture
+
–
0
votes
25
Test Series
A 32 bit machine processor has 32 register, each of which is 16 bit long. each instruction is specified with four field, namely operation part, immediate operand in addition to two register operands. assume that the immediate operand is signed integer in ... can be represented in immediate operand field is +4095. max number of instruction that can be permitted by this processor is.?
A 32 bit machine processor has 32 register, each of which is 16 bit long. each instruction is specified with four field, namely operation part, immediate operand in addit...
347
views
answered
Apr 19, 2020
CO and Architecture
co-and-architecture
+
–
0
votes
26
TANCET 2016 Lexical Analysis
Consider the following statements $S_{1}:$ The set of string described by a rule is called pattern associated with the token. $S_{2}:$ A lexeme is a sequence of character in the source program that is matched by Pattern for a token. Which of the following statement is/are true? ... $S_{2}$ is false $S_{2}$ is true $S_{1}$ is false Both $S_{1}$ and $S_{2}$ are false
Consider the following statements$S_{1}:$ The set of string described by a rule is called pattern associated with the token.$S_{2}:$ A lexeme is a sequence of character i...
4.2k
views
answered
Apr 19, 2020
Compiler Design
tancet
compiler-design
lexical-analysis
compiler-tokenization
+
–
0
votes
27
Avg stall cycles per instruction
Suppose that in $500$ memory references there are $50$ misses in the first level cache and $20$ misses in second level cache. Assume miss penalty from the $L_{2}$ cache to memory is $100$ cycles. The hit time of $L_{2}$ cache is $20$ ... $L_{1}$ cache is $10$ cycles. If there are $2.5$ memory references per instruction. How many average stall cycle per instruction?
Suppose that in $500$ memory references there are $50$ misses in the first level cache and $20$ misses in second level cache. Assume miss penalty from the $L_{2}$ cache t...
4.7k
views
answered
Apr 18, 2020
CO and Architecture
co-and-architecture
stall
cache-memory
cycle
+
–
2
votes
28
MadeEasy Test Series: CO & Architecture - Cache Memory
Suppose that in 250 memory references there are 30 misses in first level cache and 10 misses in second level cache. Assume that miss penalty from L$_2$ cache memory are 50 cycles. The hit time of L$_2$ cache is 10 cycles. The ... with given misses = 1800 stall cycles = 1800-1250 = 550 number of stalls/instruction= 550/200 = 2.75 please verify
Suppose that in 250 memory references there are 30 misses in first level cache and 10 misses in second level cache. Assume that miss penalty from L$_2$ cache memory are 5...
3.8k
views
answered
Apr 18, 2020
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
+
–
0
votes
29
GATE CSE 2020 | Question: 2
For parameters $a$ and $b$, both of which are $\omega(1)$, $T(n) = T(n^{1/a})+1$, and $T(b)=1$. Then $T(n)$ is $\Theta (\log_a \log _b n)$ $\Theta (\log_{ab} n$) $\Theta (\log_{b} \log_{a} \: n$) $\Theta (\log_{2} \log_{2} n$)
For parameters $a$ and $b$, both of which are $\omega(1)$, $T(n) = T(n^{1/a})+1$, and $T(b)=1$. Then $T(n)$ is$\Theta (\log_a \log _b n)$ $\Theta (\log_{ab} n$)$\Thet...
19.5k
views
answered
Feb 14, 2020
Algorithms
gatecse-2020
algorithms
recurrence-relation
1-mark
+
–
6
votes
30
GATE CSE 2020 | Question: 46
Consider the following C functions. int fun1(int n) { static int i= 0; if (n > 0) { ++i; fun1(n-1); } return (i); } int fun2(int n) { static int i= 0; if (n>0) { i = i+ fun1 (n) ; fun2(n-1) ; } return (i); } The return value of $\text{fun}2 (5)$ is _________
Consider the following C functions.int fun1(int n) { static int i= 0; if (n 0) { ++i; fun1(n-1); } return (i); }int fun2(int n) { static int i= ...
23.3k
views
answered
Feb 12, 2020
Programming in C
gatecse-2020
numerical-answers
programming-in-c
recursion
2-marks
+
–
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