Recent activity by sriv_shubham / GATE Overflow for GATE CSE

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GATE CSE 2017 Set 1 | Question: 27
A multithreaded program $P$ executes with $x$ number of threads and uses $y$ number of locks for ensuring mutual exclusion while operating on shared memory locations. All locks in the program are non-reentrant, i.e., if a thread holds a lock $l$, then it cannot re-acquire lock $l$ without releasing ... $x = 1, y = 2$ $x = 2, y = 1$ $x = 2, y = 2$ $x = 1, y = 1$

A multithreaded program $P$ executes with $x$ number of threads and uses $y$ number of locks for ensuring mutual exclusion while operating on shared memory locations. All...

33.4k views

commented Feb 16, 2017

11 answers

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GATE CSE 2017 Set 1 | Question: 43
Consider the following grammar: stmt $\rightarrow$ if expr then expr else expr; stmt | $Ò$ expr $\rightarrow$ term relop term | term term $\rightarrow$ id | number id $\rightarrow$ a | b | c number $\rightarrow [0-9]$ where relop is a relational ... program if $e_1$ then $e_2$ else $e_3$ has $2$ control flow paths. $e_1 \rightarrow e_2$ and $e_1 \rightarrow e_3$.

Consider the following grammar:stmt $\rightarrow$ if expr then expr else expr; stmt | $Ò$expr $\rightarrow$ term relop term | termterm $\rightarrow$ id | numberid $\righ...

20.4k views

commented Feb 15, 2017

6 answers

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GATE CSE 2017 Set 1 | Question: 31
Let $A$ be $n\times n$ real valued square symmetric matrix of rank $2$ with $\sum_{i=1}^{n}\sum_{j=1}^{n}A^{2}_{ij} = 50.$ Consider the following statements. One eigenvalue must be in $\left [ -5,5 \right ]$ The eigenvalue ... than $5$ Which of the above statements about eigenvalues of $A$ is/are necessarily CORRECT? Both I and II I only II only Neither I nor II

Let $A$ be $n\times n$ real valued square symmetric matrix of rank $2$ with $\sum_{i=1}^{n}\sum_{j=1}^{n}A^{2}_{ij} = 50.$ Consider the following statements.One eigenvalu...

49.6k views

commented Feb 14, 2017

9 answers

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GATE CSE 2017 Set 1 | Question: 25
Consider a two-level cache hierarchy with $L1$ and $L2$ caches. An application incurs $1.4$ memory accesses per instruction on average. For this application, the miss rate of $L1$ cache is $0.1$; the $L2$ cache experiences, on average, $7$ misses per $1000$ instructions. The miss rate of $L2$ expressed correct to two decimal places is ________.

Consider a two-level cache hierarchy with $L1$ and $L2$ caches. An application incurs $1.4$ memory accesses per instruction on average. For this application, the miss rat...

24.4k views

commented Feb 14, 2017

3 answers

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GATE CSE 2017 Set 1 | Question: GA-3
Rahul, Murali, Srinivas and Arul are seated around a square table. Rahul is sitting to the left of Murali. Srinivas is sitting to the right of Arul. Which of the following pairs are seated opposite each other? Rahul and Murali Srinivas and Arul Srinvas and Murali Srinivas and Rahul

Rahul, Murali, Srinivas and Arul are seated around a square table. Rahul is sitting to the left of Murali. Srinivas is sitting to the right of Arul. Which of the followin...

5.3k views

commented Feb 14, 2017

3 answers

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GATE CSE 2017 Set 1 | Question: 24
Consider the following CPU processes with arrival times (in milliseconds) and length of CPU bursts (in milliseconds) as given below: ... first scheduling algorithm is used to schedule the processes, then the average waiting time across all processes is _____________ milliseconds.

Consider the following CPU processes with arrival times (in milliseconds) and length of CPU bursts (in milliseconds) as given below:$$\small \begin{array}{|c|c|c|} \hline...

8.6k views

commented Feb 14, 2017

4 answers

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GATE CSE 2017 Set 1 | Question: 49
Consider a RISC machine where each instruction is exactly $4$ bytes long. Conditional and unconditional branch instructions use PC-relative addressing mode with Offset specified in bytes to the target location of the branch instruction. Further the Offset is ... $i,$ then the decimal value of the Offset is ____________ .

Consider a RISC machine where each instruction is exactly $4$ bytes long. Conditional and unconditional branch instructions use PC-relative addressing mode with Offset sp...

14.6k views

commented Feb 14, 2017

5 answers

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GATE CSE 2017 Set 1 | Question: GA-1
After Rajendra Chola returned from his voyage to Indonesia, he ________ to visit the temple in Thanjavur. was wishing is wishing wished had wished

After Rajendra Chola returned from his voyage to Indonesia, he ________ to visit the temple in Thanjavur.was wishingis wishingwishedhad wished

7.5k views

commented Feb 14, 2017

7 answers

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GATE CSE 2017 Set 1 | Question: 45
The values of parameters for the Stop-and-Wait ARQ protocol are as given below: Bit rate of the transmission channel $= 1$ Mbps. Propagation delay from sender to receiver $= 0.75$ ms. Time to process a frame $= 0.25$ ms. Number ... (expressed in percentage) of the Stop-and-Wait ARQ protocol for the above parameters is _____________ (correct to $2$ decimal places).

The values of parameters for the Stop-and-Wait ARQ protocol are as given below:Bit rate of the transmission channel $= 1$ Mbps.Propagation delay from sender to receiver $...

33.1k views

commented Feb 14, 2017

4 answers

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GATE CSE 2017 Set 1 | Question: 12
Consider the following intermediate program in three address code p = a - b q = p * c p = u * v q = p + q Which one of the following corresponds to a static single assignment form of the above code? p1 = a - b q1 = p1 * c p1 = u * v q1 = p1 + q1 p3 = a - b q4 = p3 * c p4 = ... = a - b q1 = p2 * c p3 = u * v q2 = p4 + q3 p1 = a - b q1 = p * c p2 = u * v q2 = p + q

Consider the following intermediate program in three address codep = a - b q = p * c p = u * v q = p + qWhich one of the following corresponds to a static single assignme...

11.6k views

answered Feb 14, 2017

7 answers

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GATE CSE 2017 Set 1 | Question: 13
Consider the following C code: #include<stdio.h> int *assignval (int *x, int val) { *x = val; return x; } void main () { int *x = malloc(sizeof(int)); if (NULL == x) return; x = assignval (x,0); ... and not as shown. compiles successfully but execution may result in dangling pointer. compiles successfully but execution may result in memory leak.

Consider the following C code:#include<stdio.h int *assignval (int *x, int val) { *x = val; return x; } void main () { int *x = malloc(sizeof(int)); if (NULL == x) return...

35.4k views

commented Feb 14, 2017

3 answers

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GATE CSE 2017 Set 1 | Question: 52
Consider the expression $(a-1) * (((b+c)/3)+d)$. Let $X$ be the minimum number of registers required by an optimal code generation (without any register spill) algorithm for a load/store architecture, in which only load and store ... memory operands and arithmetic instructions can have only register or immediate operands. The value of $X$ is _____________ .

Consider the expression $(a-1) * (((b+c)/3)+d)$. Let $X$ be the minimum number of registers required by an optimal code generation (without any register spill) algorithm ...

19.4k views

commented Feb 14, 2017

3 answers

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GATE CSE 2017 Set 1 | Question: 15
A sender $S$ sends a message $m$ to receiver $R$, which is digitally signed by $S$ with its private key. In this scenario, one or more of the following security violations can take place. $S$ ... with a fraudulent message Which of the following are possible security violations? I and II only I only II only II and III only

A sender $S$ sends a message $m$ to receiver $R$, which is digitally signed by $S$ with its private key. In this scenario, one or more of the following security violation...

12.6k views

commented Feb 14, 2017

2 answers

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GATE CSE 2017 Set 1 | Question: 23
Consider a database that has the relation schema EMP (EmpId, EmpName, and DeptName). An instance of the schema EMP and a SQL query on it are given below: ... SELECT DeptName, COUNT(EmpId) AS EC(DeptName, Num) FROM EMP GROUP BY DeptName) The output of executing the SQL query is _____________ .

Consider a database that has the relation schema EMP (EmpId, EmpName, and DeptName). An instance of the schema EMP and a SQL query on it are given below:$$\overset{\text{...

13.7k views

answered Feb 14, 2017

4 answers

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GATE CSE 2017 Set 1 | Question: 28
The value of $\displaystyle \lim_{x\rightarrow 1} \frac{x^{7}-2x^{5}+1}{x^{3}-3x^{2}+2}$ is $0$ is $-1$ is $1$ does not exist

The value of $\displaystyle \lim_{x\rightarrow 1} \frac{x^{7}-2x^{5}+1}{x^{3}-3x^{2}+2}$is $0$is $-1$is $1$does not exist

6.1k views

answered Feb 14, 2017

7 answers

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GATE CSE 2017 Set 1 | Question: 33
Consider a combination of $\text{T}$ and $\text{D}$ flip-flops connected as shown below. The output of the $\text{D}$ flip-flop is connected to the input of the $\text{T}$ flip-flop and the output of the $\text{T}$ flip-flop is connected to the input of ... $3^{\text{rd}}$ cycle are $01$ and after the $4^{\text{th}}$ cycle are $01$ respectively.

Consider a combination of $\text{T}$ and $\text{D}$ flip-flops connected as shown below. The output of the $\text{D}$ flip-flop is connected to the input of the $\text{T}...

14.8k views

answered Feb 14, 2017

6 answers

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GATE CSE 2017 Set 1 | Question: 38
Consider the following languages over the alphabet $\Sigma = \left \{ a, b, c \right \}$. Let $L_{1} = \left \{ a^{n}b^{n}c^{m}\mid m,n \geq 0 \right \}$ and $L_{2} = \left \{ a^{m}b^{n}c^{n}\mid m,n \geq 0 \right \}$. Which of the following are context-free languages? $L_{1} \cup L_{2}$ $L_{1} \cap L_{2}$ I only II only I and II Neither I nor II

Consider the following languages over the alphabet $\Sigma = \left \{ a, b, c \right \}$. Let $L_{1} = \left \{ a^{n}b^{n}c^{m}\mid m,n \geq 0 \right \}$ and $L_{2} = \le...

13.7k views

answered Feb 14, 2017

5 answers

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GATE CSE 2017 Set 1 | Question: 40
Recall that Belady's anomaly is that the page-fault rate may increase as the number of allocated frames increases. Now, consider the following statements: $S_1$: Random page replacement algorithm (where a page chosen at random is replaced) suffers from Belady's ... is true, $S_2$ is false $S_1$ is false, $S_2$ is true $S_1$ is false, $S_2$ is false

Recall that Belady's anomaly is that the page-fault rate may increase as the number of allocated frames increases. Now, consider the following statements:$S_1$: Random pa...

15.3k views

commented Feb 14, 2017

3 answers

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GATE CSE 2017 Set 1 | Question: GA-10
A contour line joins locations having the same height above the mean sea level. The following is a contour plot of a geographical region. Contour lines are shown at $25$ m intervals in this plot. If in a flood, the water level rises to $525$ m, which of the villages $P, Q, R, S, T$ get submerged? $P, Q$ $P, Q, T$ $R, S, T$ $Q, R, S$

A contour line joins locations having the same height above the mean sea level. The following is a contour plot of a geographical region. Contour lines are shown at $25$ ...

7.8k views

commented Feb 14, 2017

3 answers

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GATE CSE 2017 Set 1 | Question: 32
A computer network uses polynomials over $GF(2)$ for error checking with $8$ bits as information bits and uses $x^{3}+x+1$ as the generator polynomial to generate the check bits. In this network, the message $01011011$ is transmitted as: $01011011010$ $01011011011$ $01011011101$ $01011011100$

A computer network uses polynomials over $GF(2)$ for error checking with $8$ bits as information bits and uses $x^{3}+x+1$ as the generator polynomial to generate the che...

11.8k views

answered Feb 14, 2017

7 answers

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GATE CSE 2017 Set 1 | Question: 18
Threads of a process share global variables but not heap heap but not global variables neither global variables nor heap both heap and global variables

Threads of a process shareglobal variables but not heapheap but not global variablesneither global variables nor heapboth heap and global variables

17.2k views

commented Feb 14, 2017

8 answers

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GATE CSE 2017 Set 1 | Question: 37
Consider the context-free grammars over the alphabet $\left \{ a, b, c \right \}$ given below. $S$ and $T$ are non-terminals. $G_{1}:S\rightarrow aSb \mid T, T \rightarrow cT \mid \epsilon$ ... is Finite Not finite but regular Context-Free but not regular Recursive but not context-free

Consider the context-free grammars over the alphabet $\left \{ a, b, c \right \}$ given below. $S$ and $T$ are non-terminals.$G_{1}:S\rightarrow aSb \mid T, T \rightarrow...

12.2k views

answered Feb 14, 2017

9 answers

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GATE CSE 2017 Set 1 | Question: 47
The number of integers between $1$ and $500$ (both inclusive) that are divisible by $3$ or $5$ or $7$ is ____________ .

The number of integers between $1$ and $500$ (both inclusive) that are divisible by $3$ or $5$ or $7$ is ____________ .

11.7k views

answered Feb 14, 2017

5 answers

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GATE CSE 2017 Set 1 | Question: 26
Let $G=\left ( V,E \right )$ be $any$ connected, undirected, edge-weighted graph. The weights of the edges in $E$ are positive and distinct. Consider the following statements: Minimum Spanning Tree of $G$ is always unique. Shortest path between ... always unique. Which of the above statements is/are necessarily true? I only II only both I and II neither I nor II

Let $G=\left ( V,E \right )$ be $any$ connected, undirected, edge-weighted graph. The weights of the edges in $E$ are positive and distinct. Consider the following statem...

12.5k views

answered Feb 14, 2017

10 answers

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GATE CSE 2017 Set 1 | Question: 29
Let $p$, $q$ and $r$ be propositions and the expression $\left ( p\rightarrow q \right )\rightarrow r$ be a contradiction. Then, the expression $\left ( r\rightarrow p \right )\rightarrow q$ is a tautology a contradiction always TRUE when $p$ is FALSE always TRUE when $q$ is TRUE

Let $p$, $q$ and $r$ be propositions and the expression $\left ( p\rightarrow q \right )\rightarrow r$ be a contradiction. Then, the expression $\left ( r\rightarrow p \r...

10.7k views

answered Feb 14, 2017

10 answers

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GATE CSE 2017 Set 1 | Question: 54
A cache memory unit with capacity of $N$ words and block size of $B$ words is to be designed. If it is designed as a direct mapped cache, the length of the $\textsf{TAG}$ field is $10$ bits. If the cache unit is now designed as a $16$-way set-associative cache, the length of the $\textsf{TAG}$ field is ____________ bits.

A cache memory unit with capacity of $N$ words and block size of $B$ words is to be designed. If it is designed as a direct mapped cache, the length of the $\textsf{TAG}$...

19.7k views

answered Feb 14, 2017

10 answers

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GATE CSE 2017 Set 1 | Question: 48
Let $A$ be an array of $31$ numbers consisting of a sequence of $0$'s followed by a sequence of $1$'s. The problem is to find the smallest index $i$ such that $A\left [i \right ]$ is $1$ by probing the minimum number of locations in $A$. The worst case number of probes performed by an optimal algorithm is ____________.

Let $A$ be an array of $31$ numbers consisting of a sequence of $0$'s followed by a sequence of $1$'s. The problem is to find the smallest index $i$ such that $A\left [i ...

21.8k views

answered Feb 14, 2017

7 answers

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GATE CSE 2017 Set 1 | Question: 17
Consider the following grammar: $P\rightarrow xQRS$ $Q\rightarrow yz\mid z$ $R\rightarrow w\mid \varepsilon$ $S\rightarrow y$ What is FOLLOW($Q$)? $\left \{ R \right \}$ $\left \{ w \right \}$ $\left \{ w,y \right \}$ $\left \{ w,\$ \right \}$

Consider the following grammar:$P\rightarrow xQRS$$Q\rightarrow yz\mid z$$R\rightarrow w\mid \varepsilon$$S\rightarrow y$What is FOLLOW($Q$)?$\left \{ R \right \}$ ...

6.8k views

answered Feb 14, 2017

2 answers

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GATE CSE 2017 Set 1 | Question: 16
The following functional dependencies hold true for the relational schema $R\left \{V,W,X,Y,Z \right \}$: V $\rightarrow$ W VW $\rightarrow$ X Y $\rightarrow$ VX Y $\rightarrow$ Z Which of the following is irreducible equivalent for this set of functional ... $\rightarrow$ Z V $\rightarrow$ W W $\rightarrow$ X Y $\rightarrow$ V Y $\rightarrow$ X Y $\rightarrow$ Z

The following functional dependencies hold true for the relational schema $R\left \{V,W,X,Y,Z \right \}$:V $\rightarrow$ WVW $\rightarrow$ XY $\rightarrow$ VXY $\rightarr...

13.3k views

answered Feb 14, 2017

8 answers

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GATE CSE 2017 Set 1 | Question: 50
Instruction execution in a processor is divided into $5$ stages, Instruction Fetch (IF), Instruction Decode (ID), Operand fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10 and 3 nanoseconds (ns) ... speedup (correct to two decimal places) achieved by EP over NP in executing $20$ independent instructions with no hazards is _________ .

Instruction execution in a processor is divided into $5$ stages, Instruction Fetch (IF), Instruction Decode (ID), Operand fetch (OF), Execute (EX), and Write Back (WB). T...

19.2k views

answered Feb 14, 2017

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