Recent activity by ssanjeev24 - GATE Overflow

4 answers

1

GATE2019-33
Assume that in a certain computer, the virtual addresses are $64$ bits long and the physical addresses are $48$ bits long. The memory is word addressible. The page size is $8$ kB and the word size is $4$ bytes. The Translation Look-aside Buffer (TLB) in the address translation path has $128$ ... any TLB miss? $16 \times 2^{10}$ $256 \times 2^{10}$ $4 \times 2^{20}$ $8 \times 2^{20}$

comment edited Feb 7, 2019 in Operating System | 3.7k views

1 answer

2

Self doubt
Virtual memory increases context switching overhead ? Why why not ?

answered Jan 22, 2019 in Operating System | 71 views

0 answers

3

Self doubt
Can someone plz differentiate between: Compile time binding 2. Static binding 3. Static linking 4. Link time binding AND Dynamic binding 2. Dynamic linking 3. Run time binding

asked Jan 22, 2019 in Operating System | 27 views

3 answers

4

GATE2014-1-44
An access sequence of cache block addresses is of length $N$ and contains n unique block addresses. The number of unique block addresses between two consecutive accesses to the same block address is bounded above by $k$. What is the miss ratio if the access sequence is passed through a cache ... $\left(\dfrac{1}{N}\right)$ $\left(\dfrac{1}{A}\right)$ $\left(\dfrac{k}{n}\right)$

commented Jan 11, 2019 in CO and Architecture | 7.9k views

1 answer

5

Degree of multiprograming;SCHEDULERS
degree of multiprogramming is controlled by which scheduler and how?

commented Jul 21, 2018 in Operating System | 488 views

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