Recent activity by subho16 / GATE Overflow for GATE CSE

0 answers

1

MTech Admission
I am getting a score of 69.33(according to GO answer key and an expected rank around 200), what are the chances for me getting admissions in old IITs(top 5) ? How can I know about the procedure of admissions in IITs, whether it will be direct or interview/written test based? I want to work hard if there will be interview/test.

I am getting a score of 69.33(according to GO answer key and an expected rank around 200), what are the chances for me getting admissions in old IITs(top 5) ? How can I k...

588 views

retagged Feb 9, 2019

0 answers

2

MTech and machine learning
I am a dropper and have worked an year on machine learning in the industry. I want to do learn more about ML/AI and image processing. I am getting a rank around 200(from GO rank predictor). I am open to 2 or 3 year courses and any college is fine as long as I get to work in my field of interest and the resources are good there. What are the best options for me?

I am a dropper and have worked an year on machine learning in the industry. I want to do learn more about ML/AI and image processing. I am getting a rank around 200(from ...

828 views

asked Feb 9, 2019

1 answer

3

Speed up
Consider 3 enhancements EA, EB, and EC with speedup 30, 20, 15 respectively are applied to old system to make a new system. If enhancements EA and EB are usable for 25% of the time, then the fraction (in %) of the time must EC be used to achieve an overall speed-up of 10 is ________. (in integer form)

Consider 3 enhancements EA, EB, and EC with speedup 30, 20, 15 respectively are applied to old system to make a new system. If enhancements EA and EB are usable for 25% o...

1.9k views

answered Jan 29, 2019

4 answers

4

GATE CSE 2002 | Question: 1.9
A device employing INTR line for device interrupt puts the CALL instruction on the data bus while: $\overline{INTA}$ is active HOLD is active READY is inactive None of the above

A device employing INTR line for device interrupt puts the CALL instruction on the data bus while:$\overline{INTA}$ is activeHOLD is activeREADY is inactiveNone of the ab...

10.0k views

commented Jan 22, 2019

1 answer

5

Self doubt
Can anyone please explain in simple terms indexed, relative and base register addressing modes?

Can anyone please explain in simple terms indexed, relative and base register addressing modes?

513 views

asked Jan 19, 2019

1 answer

6

How to solve this.
Three people have 32,32,72, and $98, respectively. If they pool their money then re-distribute it among themselves, what is the maximum possible value for the median amount of money?

Three people have 32,32,72, and $98, respectively. If they pool their money then re-distribute it among themselves, what is the maximum possible value for the median amou...

571 views

answered Jan 18, 2019

6 answers

7

GATE CSE 2014 Set 1 | Question: 9
A machine has a $32\text{-bit}$ architecture, with $1\text{-word}$ long instructions. It has $64$ registers, each of which is $32$ bits long. It needs to support $45$ instructions, which have an immediate operand in ... to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ____________

A machine has a $32\text{-bit}$ architecture, with $1\text{-word}$ long instructions. It has $64$ registers, each of which is $32$ bits long. It needs to support $45$ ins...

18.4k views

commented Jan 12, 2019

0 answers

8

Doubt on syllabus
Is LU decomposition in course for GATE 2019?

Is LU decomposition in course for GATE 2019?

517 views

commented Jan 6, 2019

0 answers

9

Doubt on syllabus
Are cosets, well ordered sets, total ordered sets in syllabus or GATE 2019?

Are cosets, well ordered sets, total ordered sets in syllabus or GATE 2019?

154 views

asked Jan 6, 2019

0 answers

10

Suggestion
Can anyone tell me the relevant topics and chapters to read from Carl Hamacher book for Computer Organisation? Apart from that what can be a good source to learn CO? I have studied and revised the subject already but do not have a good understanding and have ... in solving questions. I can devote some good time for it as I am prepared for other other subjects, please answer accordingly.

Can anyone tell me the relevant topics and chapters to read from Carl Hamacher book for Computer Organisation? Apart from that what can be a good source to learn CO? I h...

664 views

asked Jan 5, 2019

0 answers

11

Self doubt
In round robin scheduling, which process gets the chance first if a process comes to ready state from running(i.e time quantom getting over) and another from new to ready(i.e due to same arrival time) ? Is there a convention or will it be specified in the question?

In round robin scheduling, which process gets the chance first if a process comes to ready state from running(i.e time quantom getting over) and another from new to ready...

398 views

asked Jan 4, 2019

0 answers

12

Self doubt
Do outputs from Mealy and Moore machines get printed only when a transition is made or are lambda transitions allowed? Putting in a different way, what will be the output if empty string is given to the machines? I have read various answers from various sources. It will be helpful if the answer has some source, any answer is welcome.

Do outputs from Mealy and Moore machines get printed only when a transition is made or are lambda transitions allowed? Putting in a different way, what will be the output...

650 views

commented Dec 22, 2018

0 answers

13

Self doubt
Hello! Can anyone point out relevant chapters from Carl Hamacher book for Computer Organisation according to GATE 2019 syllabus? I want to get my basics clear but do not want to go deep at this point of preparation. Thank you.

Hello! Can anyone point out relevant chapters from Carl Hamacher book for Computer Organisation according to GATE 2019 syllabus? I want to get my basics clear but do not ...

182 views

asked Dec 21, 2018

0 answers

14

Self doubt
I know that for a recursively enumerable language there exists an unrestricted grammar and we have formally defined unrestricted grammar. I want to know whether for every recursive language, there is a grammar or not, and if there is, is there a formal definition of the same?

I know that for a recursively enumerable language there exists an unrestricted grammar and we have formally defined unrestricted grammar. I want to know whether for every...

519 views

commented Dec 20, 2018

1 answer

15

Local Coaching
A cache is having 60% hit ratio. Cache access time is 30 ns and main memory access time is 100 ns. What is the average access time for reading? My doubt is whether to assume cache and main memory to be hierarchically connected or directly connected to the processor when nothing is given? If assumed ... , ans = 0.6(30) + 0.4(30+100). If assumed to be direct, ans = 0.6(30) + 0.4(100).

A cache is having 60% hit ratio. Cache access time is 30 ns and main memory access time is 100 ns. What is the average access time for reading?My doubt is whether to assu...

530 views

commented Nov 27, 2018

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