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Answers by suneetha

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1
Consider a two level cache system. For 100 memory references, 16 misses in the first level cache and 8 misses in the second level cache. Miss penalty from L2 cache to memory is 50 cycles. The hit time of L2 cache is 5 cycles and hit time of the L1 cache is 1 clock cycle. What is the average memory access ... x Miss penalty of L2 = ((16/ 100) x 5) + ((16/ 100) (8 / 16) x 50) = (16/ 100) (26)=4.8
answered Jan 15, 2019 in CO and Architecture 164 views
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2
Assume the scenario where size of the congestion window of a TCP connection be 40KB when timeout occurs. The MSS is 2KB. Propagation delay be 200msec. Time taken by TCP connection to get back to 40KB congestion window is …...
answered Dec 9, 2018 in Computer Networks 293 views
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3
Consider a memory access to main memory on a cache miss takes 100 ns and memory access to cache at cache hit takes 10 ns. If 75% processors memory request results in cache hit the average memory access time is _____ ns.
answered Oct 4, 2018 in CO and Architecture 267 views
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