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supreetshukla
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1
GATE CSE 2024 | Set 2 | Question: 46
A functional dependency $F: X \rightarrow Y$ is termed as a useful functional dependency if and only if it satisfies all the following three conditions: $\text{X}$ is not the empty set. $\text{Y}$ is not the empty set. Intersection ... set. For a relation $\text{R}$ with $4$ attributes, the total number of possible useful functional dependencies is __________.
A functional dependency $F: X \rightarrow Y$ is termed as a useful functional dependency if and only if it satisfies all the following three conditions:$\text{X}$ is not ...
1.5k
views
commented
Feb 25
Databases
gatecse2024-set2
numerical-answers
databases
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–
1
answer
2
GATE CSE 2024 | Set 2 | Question: 17
Which of the following statements about the Two Phase Locking ($2 \mathrm{PL}$) protocol is/are TRUE? $2 \mathrm{PL}$ permits only serializable schedules With $2 \mathrm{PL}$, a transaction always locks the data item being read or ... , no more locks on any data item can be obtained inside that transaction A deadlock is possible with $2 \mathrm{PL}$
Which of the following statements about the Two Phase Locking ($2 \mathrm{PL}$) protocol is/are TRUE?$2 \mathrm{PL}$ permits only serializable schedulesWith $...
1.8k
views
answered
Feb 16
Databases
gatecse2024-set2
databases
two-phase-locking-protocol
multiple-selects
+
–
3
answers
3
GATE CSE 2024 | Set 1 | Question: 11
In a $\mathrm{B}+$ tree, the requirement of at least half-full $(50 \%)$ node occupancy is relaxed for which one of the following cases? Only the root node All leaf nodes All internal nodes Only the leftmost leaf node
In a $\mathrm{B}+$ tree, the requirement of at least half-full $(50 \%)$ node occupancy is relaxed for which one of the following cases?Only the root nodeAll leaf nodesAl...
2.0k
views
answered
Feb 16
Databases
gatecse2024-set1
databases
+
–
1
answer
4
GATE CSE 2024 | Set 2 | Question: 29
You are given a set $V$ of distinct integers. A binary search tree $T$ is created by inserting all elements of $V$ one by one, starting with an empty tree. The tree $T$ follows the convention that, at each node, all values ... determined from $V$ Preorder traversal of $T$ can be determined from $V$ Postorder traversal of $T$ can be determined from $V$
You are given a set $V$ of distinct integers. A binary search tree $T$ is created by inserting all elements of $V$ one by one, starting with an empty tr...
1.8k
views
answered
Feb 16
Algorithms
gatecse2024-set2
algorithms
+
–
2
answers
5
GATE CSE 2024 | Set 2 | Question: 25
Let $\text{A}$ be an array containing integer values. The distance of $\text{A}$ is defined as the minimum number of elements in $\text{A}$ that must be replaced with another integer so that the resulting array is sorted in non-decreasing order. The distance of the array $[2,5,3,1,4,2,6]$ is ___________.
Let $\text{A}$ be an array containing integer values. The distance of $\text{A}$ is defined as the minimum number of elements in $\text{A}$ that must be replaced with ano...
1.9k
views
answered
Feb 16
Algorithms
gatecse2024-set2
numerical-answers
algorithms
sorting
+
–
5
answers
6
GATE CSE 2024 | Set 2 | GA Question: 4
For positive non-zero real variables $x$ and $y$, if \[ \ln \left(\frac{x+y}{2}\right)=\frac{1}{2}[\ln (x)+\ln (y)] \] then, the value of $\frac{x}{y}+\frac{y}{x}$ is $1$ $1 / 2$ $2$ $4$
For positive non-zero real variables $x$ and $y$, if\[\ln \left(\frac{x+y}{2}\right)=\frac{1}{2}[\ln (x)+\ln (y)]\]then, the value of $\frac{x}{y}+\frac{y}{x}$ is$1$$1 / ...
2.5k
views
answered
Feb 16
Quantitative Aptitude
gatecse2024-set2
quantitative-aptitude
logarithms
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–
3
answers
7
GATE CSE 2024 | Set 2 | GA Question: 10
In the $4 \times 4$ array shown below, each cell of the first three rows has either a cross $(X)$ or a number. The number in a cell represents the count of the immediate neighboring cells (left, right, top, bottom, diagonals) NOT having a cross ( $X$ ). ... has no crosses $(X)$, the sum of the four numbers to be filled in the last row is $11$ $10$ $12$ $9$
In the $4 \times 4$ array shown below, each cell of the first three rows has either a cross $(X)$ or a number.The number in a cell represents the count of the immediate n...
2.3k
views
answered
Feb 16
Analytical Aptitude
gatecse2024-set2
analytical-aptitude
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–
1
answer
8
GATE CSE 2024 | Set 2 | Question: 4
The format of a single-precision floating-point number as per the $\text{IEEE 754}$ standard is: Sign Exponent Mantissa $(1 \mathrm{bit})$ $(8 \mathrm{bits})$ $(23 \mathrm{bits})$ Choose the largest floating- ... $0$ $11111111$ $11111111111111111111111$ Sign Exponent Mantissa $0$ $01111111$ $00000000000000000000000$
The format of a single-precision floating-point number as per the $\text{IEEE 754}$ standard is:Sign ExponentMantissa$(1 \mathrm{bit})$ $(8 \mathrm{bits})$ $(23 \ma...
2.3k
views
answered
Feb 16
Digital Logic
gatecse2024-set2
digital-logic
number-representation
ieee-representation
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–
2
answers
9
GATE CSE 2024 | Set 2 | Question: 9
Once the $\text{DBMS}$ informs the user that a transaction has been successfully completed, its effect should persist even if the system crashes before all its changes are reflected on disk. This property is called durability atomicity consistency isolation
Once the $\text{DBMS}$ informs the user that a transaction has been successfully completed, its effect should persist even if the system crashes before all...
2.0k
views
answered
Feb 16
Databases
gatecse2024-set2
databases
transaction-and-concurrency
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–
1
answer
10
GATE CSE 2024 | Set 2 | Question: 10
In the context of owner and weak entity sets in the $\text{ER}$ (Entity-Relationship) data model, which one of the following statements is TRUE? The weak entity set MUST have total participation in the identifying ... in the identifying relationship Neither weak entity set nor owner entity set MUST have total participation in the identifying relationship
In the context of owner and weak entity sets in the $\text{ER}$ (Entity-Relationship) data model, which one of the following statements is TRUE?The weak entity set MUST h...
1.7k
views
answered
Feb 16
Databases
gatecse2024-set2
databases
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–
11
answers
11
GATE IT 2007 | Question: 24
A depth-first search is performed on a directed acyclic graph. Let $d[u]$ denote the time at which vertex $u$ is visited for the first time and $f[u]$ the time at which the DFS call to the vertex $u$ terminates. Which of the following statements is always TRUE for all edges $(u, v)$ in the graph ? $d[u] < d[v]$ $d[u] < f[v]$ $f[u] < f[v]$ $f[u] > f[v]$
A depth-first search is performed on a directed acyclic graph. Let $d[u]$ denote the time at which vertex $u$ is visited for the first time and $f[u]$ the time at which t...
13.5k
views
answered
Jan 30, 2023
Algorithms
gateit-2007
algorithms
graph-algorithm
normal
graph-search
depth-first-search
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–
1
answer
12
back edge and no forward edge
Which does this sentence mean? In BFS of an undirected graph, there are no back edge and no forward edge.
Which does this sentence mean?In BFS of an undirected graph, there are no back edge and no forward edge.
2.5k
views
answered
Jan 29, 2023
DS
programming-in-c
data-structures
breadth-first-search
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–
1
answer
13
Applied Gate Test Series
340
views
answered
Jan 25, 2023
CO and Architecture
pipelining
computer-architecture
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–
5
answers
14
GATE CSE 2022 | Question: 51
A processor $\text{X}_{1}$ operating at $2 \; \text{GHz}$ has a standard $5-$stage $\text{RISC}$ instruction pipeline having a base $\text{CPI (cycles per instruction)}$ of one without any pipeline hazards. For a given program $\text{P}$ ... $\text{X}_{2}$ over $\text{X}_{1}$ in executing $\text{P}$ is _______________.
A processor $\text{X}_{1}$ operating at $2 \; \text{GHz}$ has a standard $5-$stage $\text{RISC}$ instruction pipeline having a base $\text{CPI (cycles per instruction)}$ ...
9.9k
views
answer edited
Jan 25, 2023
CO and Architecture
gatecse-2022
numerical-answers
co-and-architecture
pipelining
stall
2-marks
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–
3
answers
15
Made easy Gate mock test -1
A Boolean Function must satisfy the condition f(a,b,c) = f(c,b,a). how many such functions are possible?
A Boolean Function must satisfy the condition f(a,b,c) = f(c,b,a). how many such functions are possible?
778
views
commented
Jan 24, 2023
Digital Logic
numerical-answers
digital-logic
made-easy-test-series
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–
1
answer
16
Zeal Test
Question : Consider a system with 20 bit physical address and direct mapped cache with 64 blocks and block size of 16 bytes To what block number does byte address 1200 mapped??
Question :Consider a system with 20 bit physical address and direct mapped cache with 64 blocks and block size of 16 bytes To what block number does byte address 1200 map...
698
views
answer edited
Jan 19, 2023
CO and Architecture
co-and-architecture
zeal
cache-memory
direct-mapping
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–
14
answers
17
GATE CSE 2008 | Question: 67
A processor uses $36$ bit physical address and $32$ bit virtual addresses, with a page frame size of $4$ Kbytes. Each page table entry is of size $4$ bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as ... tables are respectively $\text{20,20,20}$ $\text{24,24,24}$ $\text{24,24,20}$ $\text{25,25,24}$
A processor uses $36$ bit physical address and $32$ bit virtual addresses, with a page frame size of $4$ Kbytes. Each page table entry is of size $4$ bytes. A three level...
75.7k
views
answered
Jan 17, 2023
Operating System
gatecse-2008
operating-system
virtual-memory
normal
+
–
4
answers
18
Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 19 (Page No. 256)
A computer with a $32-bit$ address uses a two-level page table. Virtual addresses are split into a $9-bit$ top-level page table field, an $11-bit$ second-level page table field, and an offset. How large are the pages and how many are there in the address space?
A computer with a $32-bit$ address uses a two-level page table. Virtual addresses are split into a $9-bit$ top-level page table field, an $11-bit$ second-level page table...
2.5k
views
commented
Jan 17, 2023
Operating System
tanenbaum
operating-system
memory-management
multilevel-paging
paging
descriptive
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–
2
answers
19
gate applied mock test -3
Suppose that you wish to design a virtual memory system with the following characteristics: i. The size of a page table entry is 4 bytes. ii. Each page table must fit into a single physical frame. iii. The system must be able to support virtual address ... no more than two levels of page tables. What is the minimum page size that your system must have? 8KB 16KB 32KB none
Suppose that you wish to design a virtual memory system with the following characteristics:i. The size of a page table entry is 4 bytes.ii. Each page table must fit into ...
859
views
answered
Jan 17, 2023
Operating System
multilevel-paging
virtual-memory
+
–
1
answer
20
Virtual Gate Test Series: Digital Logic - Carry Look Ahead Adder
In a $4-$bit carry look ahead adder, the propagation delay of EX-OR gate is $20ns,$ AND and OR gates is $10ns.$ The sum and carry output of full adder takes $20ns$ and $10ns$ respectively. The total propagation delay of the above adder in $ns$ is
In a $4-$bit carry look ahead adder, the propagation delay of EX-OR gate is $20ns,$ AND and OR gates is $10ns.$ The sum and carry output of full adder takes $20ns$ and $1...
802
views
answered
Jan 4, 2023
Digital Logic
digital-logic
combinational-circuit
carry-look-ahead-adder
virtual-gate-test-series
+
–
3
answers
21
Applied test series question
A 4-bit carry lookahead adder adds two 4-bit numbers. The adder is designed without making use of the EX-OR gates. The propagation delay for all gates is given as 2.4 time units. What will be the overall delay of adder if we assume that inputs ... AND, Or gates. can someone explain me this in a deatiled manner as i am not able to find the appropriate solution for it ?
A 4-bit carry lookahead adder adds two 4-bit numbers. The adder is designed without making use of the EX-OR gates. The propagation delay for all gates is given as 2.4 tim...
600
views
answered
Jan 4, 2023
Digital Logic
test-series
digital-logic
adder
+
–
2
answers
22
UGC NET CSE | October 2022 | Part 1 | Question: 45
Match List I with List II : List I List II (A) Type $0$ (I) Finite automata (B) Type $1$ (II) Tuning machine (C) Type $2$ (III) Linear bound automata (D) Type $3$ ...
Match List I with List II :List IList II(A) Type $0$(I) Finite automata(B) Type $1$(II) Tuning machine(C) Type $2$(III) Linear bound automata(D) Type $3$(IV) Pushdown aut...
598
views
answered
Nov 15, 2022
Others
ugcnetcse-oct2022-paper1
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–
1
answer
23
UGC NET CSE | October 2022 | Part 1 | Question: 59
Match List I with List II : ... $\text{(A)-(II), (B)-(I), (C)-(Iii), (D)-(IV)}$
Match List I with List II :$\begin{array}{ll} \text{List I} & \text{List II} \\ \\\text { (A) Least frequently used } & \text { (I) Memory is distributed among processors...
499
views
answered
Nov 15, 2022
Operating System
ugcnetcse-oct2022-paper1
operating-system
+
–
2
answers
24
igate test series
The instruction pipeline of RISC processor has 200 instruction in which 100 are performing addition, 25 performing division and 75 are performing multiplication, where Execution state for addition take 1 clock, multiplication take 3 clock cycles and division take 5 clock cycles. Assume pipeline ... wrong. approch totel 200 in which (100 add having 1 cc) +(25*5-1) +(75*(3-1))=354
The instruction pipeline of RISC processor has 200 instruction in which 100 are performing addition, 25 performing division and 75 are performing multiplication, where Ex...
453
views
answered
Oct 1, 2022
CO and Architecture
co-and-architecture
pipelining
numerical-answers
i-gate-test-series
+
–
11
answers
25
GATE CSE 2016 Set 1 | Question: 55
A sender uses the Stop-and-Wait $\text{ARQ}$ protocol for reliable transmission of frames. Frames are of size $1000$ ... $100$ milliseconds. Assuming no frame is lost, the sender throughput is ________ bytes/ second.
A sender uses the Stop-and-Wait $\text{ARQ}$ protocol for reliable transmission of frames. Frames are of size $1000$ bytes and the transmission rate at the sender is $80\...
26.1k
views
answered
Aug 19, 2022
Computer Networks
gatecse-2016-set1
computer-networks
stop-and-wait
normal
numerical-answers
+
–
2
answers
26
GATE CSE 2012 | Question: 54
A computer has a $256\text{-KByte}$, 4-way set associative, write back data cache with block size of $32\text{-Bytes}$. The processor sends $32\text{-bit}$ ... bit and $1$ replacement bit. The number of bits in the tag field of an address is $11$ $14$ $16$ $27$
A computer has a $256\text{-KByte}$, 4-way set associative, write back data cache with block size of $32\text{-Bytes}$. The processor sends $32\text{-bit}$ addresses to t...
22.0k
views
commented
Aug 10, 2022
CO and Architecture
gatecse-2012
co-and-architecture
cache-memory
normal
+
–
3
answers
27
Applied Test Series
A fair coin is tossed 20 times. The probability of getting the three or more heads in a row is 0.7870 and the probability of getting three or more heads in a row or three or more tails in a row is 0.9791. What is the probability of getting three or more heads in a row and three or more tails in a row________
A fair coin is tossed 20 times. The probability of getting the three or more heads in a row is 0.7870 and the probability of getting three or more heads in a row or three...
3.2k
views
answered
Feb 1, 2022
1
answer
28
max weighted MST possible
Let G be a complete undirected graph on 5 vertices 10 edges, with weights being 1, 2, 3, 4, 5, 6, 7, 8, 9, 10. Let X be the value of the maximum possible weight a MST of G can have. Then the value of x will be_____ the answer to this question is given as 11 but there is no procedure given . Please ,can anyone help me out in understanding the procedure
Let G be a complete undirected graph on 5 vertices 10 edges, with weights being 1, 2, 3, 4, 5, 6, 7, 8, 9, 10. Let X be the value of the maximum possible weight a MST o...
719
views
answered
Jan 15, 2022
Graph Theory
minimum-spanning-tree
+
–
3
answers
29
Job Sequencing Problem (Greedy Algorithm)
If job $J=(J_{1},J_{2},J_{3},J_{4})$ are given their processing time $T_{i}=(1,1,2,3)$ and deadline are $D_{i}=(3,4,2,3)$ maximum how many job can be done$?$ $A)1$ $B)2$ $C)3$ $D)All$
If job $J=(J_{1},J_{2},J_{3},J_{4})$ are given their processing time $T_{i}=(1,1,2,3)$ and deadline are $D_{i}=(3,4,2,3)$ maximum how many job can be done$?$$A)1$ ...
12.3k
views
answered
Jan 15, 2022
Algorithms
algorithms
greedy-algorithm
algorithm-design
job-scheduling
+
–
2
answers
30
MadeEasy Test Series: Digital Logic - K Map
795
views
answer edited
Nov 14, 2021
Digital Logic
made-easy-test-series
digital-logic
minimization
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