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Recent activity by supreetshukla

11 answers
1
GATE IT 2007 | Question: 24
A depth-first search is performed on a directed acyclic graph. Let $d[u]$ denote the time at which vertex $u$ is visited for the first time and $f[u]$ the time at which the DFS call to the vertex $u$ terminates. Which of the following statements is always TRUE for all edges $(u, v)$ in the graph ? $d[u] < d[v]$ $d[u] < f[v]$ $f[u] < f[v]$ $f[u] > f[v]$
answered in Algorithms Jan 30
10.9k views
  • gateit-2007
  • algorithms
  • graph-algorithms
  • normal
  • graph-search
2 answers
2
back edge and no forward edge
Which does this sentence mean? In BFS of an undirected graph, there are no back edge and no forward edge.
answered in DS Jan 29
2.1k views
  • programming-in-c
  • data-structures
  • breadth-first-search
1 answer
3
Applied Gate Test Series
answered in CO and Architecture Jan 25
211 views
  • pipelining
  • computer-architecture
5 answers
4
GATE CSE 2022 | Question: 51
A processor $\text{X}_{1}$ operating at $2 \; \text{GHz}$ has a standard $5-$stage $\text{RISC}$ instruction pipeline having a base $\text{CPI (cycles per instruction)}$ of one without any pipeline hazards. For a given program $\text{P}$ ... $\text{X}_{2}$ over $\text{X}_{1}$ in executing $\text{P}$ is _______________.
answer edited in CO and Architecture Jan 25
5.1k views
  • gatecse-2022
  • numerical-answers
  • co-and-architecture
  • pipelining
  • stall
  • 2-marks
3 answers
5
Made easy Gate mock test -1
A Boolean Function must satisfy the condition f(a,b,c) = f(c,b,a). how many such functions are possible?
commented in Digital Logic Jan 24
430 views
  • numerical-answers
  • digital-logic
  • made-easy-test-series
1 answer
6
Zeal Test
Question : Consider a system with 20 bit physical address and direct mapped cache with 64 blocks and block size of 16 bytes To what block number does byte address 1200 mapped??
answer edited in CO and Architecture Jan 19
366 views
  • co-and-architecture
  • zeal
  • cache-memory
  • direct-mapping
13 answers
7
GATE CSE 2008 | Question: 67
A processor uses $36$ bit physical address and $32$ bit virtual addresses, with a page frame size of $4$ Kbytes. Each page table entry is of size $4$ bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as ... tables are respectively $\text{20,20,20}$ $\text{24,24,24}$ $\text{24,24,20}$ $\text{25,25,24}$
answered in Operating System Jan 17
64.3k views
  • gatecse-2008
  • operating-system
  • virtual-memory
  • normal
4 answers
8
Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 19 (Page No. 256)
A computer with a $32-bit$ address uses a two-level page table. Virtual addresses are split into a $9-bit$ top-level page table field, an $11-bit$ second-level page table field, and an offset. How large are the pages and how many are there in the address space?
commented in Operating System Jan 17
1.5k views
  • tanenbaum
  • operating-system
  • memory-management
  • multilevel-paging
  • paging
  • descriptive
2 answers
9
gate applied mock test -3
Suppose that you wish to design a virtual memory system with the following characteristics: i. The size of a page table entry is 4 bytes. ii. Each page table must fit into a single physical frame. iii. The system must be able to support virtual address ... no more than two levels of page tables. What is the minimum page size that your system must have? 8KB 16KB 32KB none
answered in Operating System Jan 17
636 views
  • multilevel-paging
  • virtual-memory
1 answer
10
Virtual Gate Test Series: Digital Logic - Carry Look Ahead Adder
In a $4-$bit carry look ahead adder, the propagation delay of EX-OR gate is $20ns,$ AND and OR gates is $10ns.$ The sum and carry output of full adder takes $20ns$ and $10ns$ respectively. The total propagation delay of the above adder in $ns$ is
answered in Digital Logic Jan 4
528 views
  • digital-logic
  • combinational-circuit
  • carry-look-ahead-adder
  • virtual-gate-test-series
3 answers
11
Applied test series question
A 4-bit carry lookahead adder adds two 4-bit numbers. The adder is designed without making use of the EX-OR gates. The propagation delay for all gates is given as 2.4 time units. What will be the overall delay of adder if we assume that inputs ... AND, Or gates. can someone explain me this in a deatiled manner as i am not able to find the appropriate solution for it ?
answered in Digital Logic Jan 4
344 views
  • test-series
  • digital-logic
  • adder
2 answers
12
UGC NET CSE | October 2022 | Part 1 | Question:: 45
Match List I with List II : List I List II (A) Type $0$ (I) Finite automata (B) Type $1$ (II) Tuning machine (C) Type $2$ (III) Linear bound automata (D) Type $3$ ...
answered in Others Nov 15, 2022
223 views
  • ugcnetcse-oct2022-paper1
1 answer
13
UGC NET CSE | October 2022 | Part 1 | Question:: 59
Match List I with List II : ... $\text{(A)-(II), (B)-(I), (C)-(Iii), (D)-(IV)}$
answered in Operating System Nov 15, 2022
162 views
  • ugcnetcse-oct2022-paper1
  • operating-system
2 answers
14
igate test series
The instruction pipeline of RISC processor has 200 instruction in which 100 are performing addition, 25 performing division and 75 are performing multiplication, where Execution state for addition take 1 clock, multiplication take 3 clock cycles and division take 5 clock cycles. Assume pipeline ... wrong. approch totel 200 in which (100 add having 1 cc) +(25*5-1) +(75*(3-1))=354
answered in CO and Architecture Oct 1, 2022
269 views
  • co-and-architecture
  • pipelining
  • numerical-answers
  • i-gate-test-series
11 answers
15
GATE CSE 2016 Set 1 | Question: 55
A sender uses the Stop-and-Wait $\text{ARQ}$ protocol for reliable transmission of frames. Frames are of size $1000$ ... $100$ milliseconds. Assuming no frame is lost, the sender throughput is ________ bytes/ second.
answered in Computer Networks Aug 19, 2022
21.3k views
  • gatecse-2016-set1
  • computer-networks
  • stop-and-wait
  • normal
  • numerical-answers
2 answers
16
GATE CSE 2012 | Question: 54
A computer has a $256\text{-KByte}$, 4-way set associative, write back data cache with block size of $32\text{-Bytes}$. The processor sends $32\text{-bit}$ ... bit and $1$ replacement bit. The number of bits in the tag field of an address is $11$ $14$ $16$ $27$
commented in CO and Architecture Aug 10, 2022
18.5k views
  • gatecse-2012
  • co-and-architecture
  • cache-memory
  • normal
3 answers
17
Applied Test Series
A fair coin is tossed 20 times. The probability of getting the three or more heads in a row is 0.7870 and the probability of getting three or more heads in a row or three or more tails in a row is 0.9791. What is the probability of getting three or more heads in a row and three or more tails in a row________
answered in Mathematical Logic Feb 1, 2022
2.3k views
1 answer
18
max weighted MST possible
Let G be a complete undirected graph on 5 vertices 10 edges, with weights being 1, 2, 3, 4, 5, 6, 7, 8, 9, 10. Let X be the value of the maximum possible weight a MST of G can have. Then the value of x will be_____ the answer to this question is given as 11 but there is no procedure given . Please ,can anyone help me out in understanding the procedure
answered in Graph Theory Jan 15, 2022
536 views
  • minimum-spanning-tree
3 answers
19
Job Sequencing Problem (Greedy Algorithm)
If job $J=(J_{1},J_{2},J_{3},J_{4})$ are given their processing time $T_{i}=(1,1,2,3)$ and deadline are $D_{i}=(3,4,2,3)$ maximum how many job can be done$?$ $A)1$ $B)2$ $C)3$ $D)All$
answered in Algorithms Jan 15, 2022
10.3k views
  • algorithms
  • greedy-algorithm
  • algorithm-design
  • job-scheduling
2 answers
20
MadeEasy Test Series: Digital Logic - K Map
answer edited in Digital Logic Nov 14, 2021
592 views
  • made-easy-test-series
  • digital-logic
  • minimization
5 answers
21
TIFR CSE 2018 | Part A | Question: 7
Consider the following function definition. void greet(int n) { if(n>0) { printf("hello"); greet(n-1); } printf("world"); } If you run $\textsf{greet(n)}$ ... "helloworld" $\textsf{n+1}$ times "helloworld" $\textsf{n}$ times "helloworld", followed by "world"
answered in Programming Apr 11, 2021
2.4k views
  • tifr2018
  • programming
  • programming-in-c
  • recursion

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