# Recent activity by swagnikd

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Let $P_1, P_2,\dots , P_n$be $n$ points in the $xy$-plane such that no three of them are collinear. For every pair of points $P_i$ and $P_j$, let $L_{ij}$ be the line passing through them. Let $L_{ab}$ be the line with the steepest gradient among all $n(n -1)/2$ lines. The ... and $P_b$ is $\Theta\left(n\right)$ $\Theta\left(n\log n\right)$ $\Theta\left(n\log^2 n\right)$ $\Theta\left(n^2\right)$
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A binary tree with $n > 1$ nodes has $n_1$, $n_2$ and $n_3$ nodes of degree one, two and three respec­tively. The degree of a node is defined as the number of its neighbours. $n_3$ can be expressed as $n_1 + n_2 - 1$ $n_1 -2$ $[((n_1 + n_2)/2)]$ $n_2 - 1$
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The least number of temporary variables required to create a three-address code in static single assignment form for the expression $q + r / 3 + s - t * 5 + u * v/w$ is__________________.
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A grammar that is both left and right recursive for a non-terminal, is Ambiguous Unambiguous Information is not sufficient to decide whether it is ambiguous or unambiguous None of the above
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When an interrupt occurs, an operating system ignores the interrupt always changes state of interrupted process after processing the interrupt always resumes execution of interrupted process after processing the interrupt may change state of interrupted process to ‘blocked’ and schedule another process.
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Why last host of last subnet is 11011110 and not 11111110 ? How many max subnets it can have in 3 bits?
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explain!
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Consider a machine with a $2$-way set associative data cache of size $64$ Kbytes and block size $16$ bytes. The cache is managed using $32$ bit virtual addresses and the page size is $4$ Kbytes. A program to be run on this machine begins as follows: double ARR; int i, j; /*Initialize ... elements have the same cache index as $ARR$? $ARR$ $ARR$ $ARR$ $ARR$
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An instruction pipeline consists of following 5 stages: IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MA = Memory Access and WB = Register Write Back. Now consider the following code: 1. LOAD R8, 0(R5); R8 = memory [R5] 2. LOAD R9, 4 ... cycle for all the instructions. How many cycles are required to execute the code, without operand forwarding over a bypass network? 9 10 11 14
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Consider a machine with a byte addressable main memory of $2^{16}$ bytes. Assume that a direct mapped data cache consisting of $32$ lines of $64$ $bytes$ each is used in the system. A $50$ x $50$ two-dimensional array of bytes is stored in the main memory starting from ... of the data cache do not change in between the two accesses. How many data misses will occur in total? $48$ $50$ $56$ $59$
Which of the following query transformations (i.e., replacing the l.h.s. expression by the r.h.s expression) is incorrect? R1 and R2 are relations, C1 and C2 are selection conditions and A1 and A2 are attributes of R1. A. ... $\pi_{A_1} \left(\sigma_{C_1}\left(R_1\right)\right) \to \sigma_{C_1} \left(\pi_{A_1}\left(R_1\right)\right)$
What is the return value of $f(p,p)$, if the value of $p$ is initialized to $5$ before the call? Note that the first parameter is passed by reference, whereas the second parameter is passed by value. int f (int &x, int c) { c = c - 1; if (c==0) return 1; x = x + 1; return f(x,c) * x; }
Let R and S be two relations with the following schema $R(\underline{P,Q}, R1, R2, R3)$ $S(\underline{P,Q}, S1, S2)$ where $\left\{P, Q\right\}$ is the key for both schemas. Which of the following queries are equivalent? $\Pi_P \left(R \bowtie S\right)$ ... Only I and II Only I and III Only I, II and III Only I, III and IV