Recent activity by swagnikd / GATE Overflow for GATE CSE

6 answers

1

GATE IT 2007 | Question: 81
Let $P_1, P_2,\dots , P_n $be $n$ points in the $xy$-plane such that no three of them are collinear. For every pair of points $P_i$ and $P_j$, let $L_{ij}$ be the line passing through them. Let $L_{ab}$ ... $\Theta\left(n\right)$ $\Theta\left(n\log n\right)$ $\Theta\left(n\log^2 n\right)$ $\Theta\left(n^2\right)$

Let $P_1, P_2,\dots , P_n $be $n$ points in the $xy$-plane such that no three of them are collinear. For every pair of points $P_i$ and $P_j$, let $L_{ij}$ be the line pa...

6.3k views

answered Jan 4, 2017

5 answers

2

GATE IT 2008 | Question: 76
A binary tree with $n > 1$ nodes has $n_1$, $n_2$ and $n_3$ nodes of degree one, two and three respectively. The degree of a node is defined as the number of its neighbours. $n_3$ can be expressed as $n_1 + n_2 - 1$ $n_1 -2$ $[((n_1 + n_2)/2)]$ $n_2 - 1$

A binary tree with $n 1$ nodes has $n_1$, $n_2$ and $n_3$ nodes of degree one, two and three respectively. The degree of a node is defined as the number of its neighbo...

17.0k views

answered Dec 27, 2016

7 answers

3

GATE CSE 2015 Set 1 | Question: 55
The least number of temporary variables required to create a three-address code in static single assignment form for the expression $q + r / 3 + s - t * 5 + u * v/w$ is__________________.

The least number of temporary variables required to create a three-address code in static single assignment form for the expression $q + r / 3 + s - t * 5 + u * v/w$ is_...

29.1k views

commented Dec 20, 2016

2 answers

4

GATE CSE 1999 | Question: 2.15
A grammar that is both left and right recursive for a non-terminal, is Ambiguous Unambiguous Information is not sufficient to decide whether it is ambiguous or unambiguous None of the above

A grammar that is both left and right recursive for a non-terminal, isAmbiguousUnambiguousInformation is not sufficient to decide whether it is ambiguous or unambiguousNo...

9.7k views

answered Dec 19, 2016

4 answers

5

GATE CSE 1997 | Question: 3.8
When an interrupt occurs, an operating system ignores the interrupt always changes state of interrupted process after processing the interrupt always resumes execution of interrupted process after processing the interrupt may change state of interrupted process to ‘blocked’ and schedule another process.

When an interrupt occurs, an operating systemignores the interruptalways changes state of interrupted process after processing the interruptalways resumes execution of in...

13.9k views

answered Dec 9, 2016

1 answer

6

IP addressing
Why last host of last subnet is 11011110 and not 11111110 ? How many max subnets it can have in 3 bits?

Why last host of last subnet is 11011110 and not 11111110 ? How many max subnets it can have in 3 bits?

967 views

commented Dec 3, 2016

3 answers

7

testbook_os
explain!

explain!

333 views

answered Nov 6, 2016

6 answers

8

GATE CSE 2008 | Question: 72
Consider a machine with a $2$-way set associative data cache of size $64$ Kbytes and block size $16$ bytes. The cache is managed using $32$ bit virtual addresses and the page size is $4$ Kbytes. A program to be run on this machine begins as follows: double ARR[1024][1024]; int i, j; ... $\text{ARR[0][4]}$ $\text{ARR[4][0]}$ $\text{ARR[0][5]}$ $\text{ARR[5][0]}$

Consider a machine with a $2$-way set associative data cache of size $64$ Kbytes and block size $16$ bytes. The cache is managed using $32$ bit virtual addresses and the ...

15.7k views

commented Nov 3, 2016

2 answers

9

MadeEasy Test Series: CO & Architecture - Pipelining
An instruction pipeline consists of following 5 stages: IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MA = Memory Access and WB = Register Write Back. Now consider the following code: 1. LOAD R8, 0(R5); ... instructions. How many cycles are required to execute the code, without operand forwarding over a bypass network? 9 10 11 14

An instruction pipeline consists of following 5 stages:IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MA = Memory Access and WB = Register Write Back.Now ...

5.6k views

commented Oct 31, 2016

10 answers

10

GATE CSE 2007 | Question: 80
Consider a machine with a byte addressable main memory of $2^{16}$ bytes. Assume that a direct mapped data cache consisting of $32$ lines of $64$ bytes each is used in the system. A $50 \times 50$ two-dimensional array of bytes is stored in the main ... data cache do not change in between the two accesses. How many data misses will occur in total? $48$ $50$ $56$ $59$

Consider a machine with a byte addressable main memory of $2^{16}$ bytes. Assume that a direct mapped data cache consisting of $32$ lines of $64$ bytes each is used in th...

32.6k views

commented Oct 24, 2016

6 answers

11

GATE CSE 1998 | Question: 2.19
Which of the following query transformations (i.e., replacing the l.h.s. expression by the r.h.s expression) is incorrect? R1 and R2 are relations, C1 and C2 are selection conditions and A1 and A2 are attributes of R1. ... $\pi_{A_1} \left(\sigma_{C_1}\left(R_1\right)\right) \to \sigma_{C_1} \left(\pi_{A_1}\left(R_1\right)\right)$

Which of the following query transformations (i.e., replacing the l.h.s. expression by the r.h.s expression) is incorrect? R1 and R2 are relations, C1 and C2 are selectio...

17.3k views

comment edited Sep 3, 2016

2 answers

12

GATE CSE 2013 | Question: 42
What is the return value of $f(p,p)$, if the value of $p$ is initialized to $5$ before the call? Note that the first parameter is passed by reference, whereas the second parameter is passed by value. int f (int &x, int c) { c = c - 1; if (c==0) return 1; x = x + 1; return f(x,c) * x; }

What is the return value of $f(p,p)$, if the value of $p$ is initialized to $5$ before the call? Note that the first parameter is passed by reference, whereas the second ...

21.2k views

commented Aug 31, 2016

4 answers

13

GATE CSE 2008 | Question: 68
Let R and S be two relations with the following schema $R(\underline{P,Q}, R1, R2, R3)$ $S(\underline{P,Q}, S1, S2)$ where $\left\{P, Q\right\}$ is the key for both schemas. Which of the following queries are equivalent? $\Pi_P \left(R \bowtie S\right)$ ... Only I and II Only I and III Only I, II and III Only I, III and IV

Let R and S be two relations with the following schema$R(\underline{P,Q}, R1, R2, R3)$$S(\underline{P,Q}, S1, S2)$where $\left\{P, Q\right\}$ is the key for both schemas....

18.1k views

answered Aug 31, 2016

1 answer

14

Type of Grammar
What type of grammar is this most accurately described as? S-> b/ aD D-> a/ aDD A. A regular grammar B. CFG C. CSG D. Type-0

What type of grammar is this most accurately described as?S- b/ aDD- a/ aDDA. A regular grammar B. CFG C. CSG D. Type-0

4.9k views

commented Apr 13, 2016

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