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2 votes
61
CFL or DCFL or Not CFL
Which are DCFL, CFL, or not CFL 1. ambnck 2. ambnck | m=n or n=k if m=even then m=k 3. ambnck | if m=n then n=k
Which are DCFL, CFL, or not CFL1. ambnck2. ambnck | m=n or n=k if m=even then m=k3. ambnck | if m=n then n=k
0 votes
62
GATE CSE 1989 | Question: 4-ix
Explain the behaviour of the following logic circuit with level input $A$ and output $B$.
Explain the behaviour of the following logic circuit with level input $A$ and output $B$.
0 votes
63
process synchronisation
1 votes
64
Aptitude
A with the help of a son can do a work in 10days . They start together and after 6 days his son left the work . Then remaining work will be done by A in 8 days . Then A alone would do work in how many days ? verify please :)
A with the help of a son can do a work in 10days . They start together and after 6 days his son left the work . Then remaining work will be done by A in 8 days . Then A a...
2 votes
65
context free grammar
Is L2 same as a^i b^j c^j , i,j >=0?
Is L2 same as a^i b^j c^j , i,j >=0?
3 votes
66
minimised Automata
Let $L=\{(a^p)^* \mid$ p is a prime number$\}$ and $\Sigma=\{a\}$ .The minimum number of states in NFA that accepts $L$ is?
Let $L=\{(a^p)^* \mid$ p is a prime number$\}$ and $\Sigma=\{a\}$ .The minimum number of states in NFA that accepts $L$ is?
1 votes
68
GATE CSE 1987 | Question: 13-a
The below figure shows four $\text{D}$-type flip-flops connected as a shift register using a $\text{XOR}$ ... $Q_{A} Q_{B} Q_{C} Q_{D}$ after the fourth clock pulse is $0000$ $1111$ $1001$ $1000$
The below figure shows four $\text{D}$-type flip-flops connected as a shift register using a $\text{XOR}$ gate. The initial state and three subsequent states for three cl...
5 votes
70
Compiler Design LR(0) Checking
Is E --> E+T / T , T --> i is LR(0) grammar ?
Is E E+T / T , T i is LR(0) grammar ?
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