Recent activity by topper98 / GATE Overflow for GATE CSE

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GATE Mechanical 2020 Set 2 | GA Question: 6
Climate change and resilience deal with two aspects - reduction of sources of non-renewable energy resources and reducing vulnerability of climate change aspects. The terms mitigation' and adaptation' are used to refer to these aspects, ... taken to reduce the use of fossil fuels. Adaptation deals with actions taken to combat green-house gas emissions

Climate change and resilience deal with two aspects – reduction of sources of non-renewable energy resources and reducing vulnerability of climate change aspects. The t...

487 views

commented Jun 8, 2021

1 answer

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NIELIT 2017 DEC Scientist B - Section B: 7
Let $G$ be a grammar in CFG and let $W_1,W_2\in L(G)$ such that $\mid W_1\mid=\mid W_2\mid$ then which of the following statements is true? Any derivation of $W_1$ has exactly the same number of steps as any derivation ... $W_1$ may be shorter than the derivation of $W_2$ None of the options

Let $G$ be a grammar in CFG and let $W_1,W_2\in L(G)$ such that $\mid W_1\mid=\mid W_2\mid$ then which of the following statements is true?Any derivation of $W_1$ has exa...

1.1k views

answer edited Aug 2, 2020

3 answers

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NIELIT 2017 DEC Scientist B - Section B: 8
Let $A$ be an array of $31$ numbers consisting of a sequence of $0$’s followed by a sequence of $1$’s. The problem is to find the smallest index $i$ such that $A[i]$ is $1$ by probing the minimum number of locations in $A$. The worst case number of probes performed by an optimal algorithm is $2$ $4$ $3$ $5$

Let $A$ be an array of $31$ numbers consisting of a sequence of $0$’s followed by a sequence of $1$’s. The problem is to find the smallest index $i$ such that $A[i]$ ...

1.1k views

answered Jun 15, 2020

4 answers

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NIELIT 2017 DEC Scientist B - Section B: 5
Which of the following is machine independent optimization? Loop optimization Redundancy Elimination Folding All of the option

Which of the following is machine independent optimization?Loop optimizationRedundancy EliminationFoldingAll of the option

8.9k views

answered Jun 15, 2020

7 answers

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GATE CSE 2008 | Question: 38
In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is: before effective address calculation has started during effective address calculation after effective address calculation has completed after data cache lookup has completed

In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is:before effective address calculation has starteddur...

19.4k views

answered Jun 5, 2020

1 answer

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CisternPipes
A tank is filled by three pipes with uniform flow. The first two pipes operating simultaneously fill the tank in the same time during which the tank is filled by the third pipe alone. The second pipe fills the tank 5 hours faster than the first pipe and 4 hours slower than the third pipe. The time required by the first pipe is: A. 6 hours B. 10 hours C. 15 hours D. 30 hours

A tank is filled by three pipes with uniform flow. The first two pipes operating simultaneously fill the tank in the same time during which the tank is filled by the thir...

1.3k views

commented Jun 2, 2020

5 answers

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GATE CSE 2003 | Question: 10, ISRO-DEC2017-41
For a pipelined CPU with a single ALU, consider the following situations The ${j+1}^{st}$ instruction uses the result of the $j^{th}$ instruction as an operand The execution of a conditional jump instruction The $j^{th}$ and ${j+1}^{st}$ ... ALU at the same time. Which of the above can cause a hazard I and II only II and III only III only All the three

For a pipelined CPU with a single ALU, consider the following situationsThe ${j+1}^{st}$ instruction uses the result of the $j^{th}$ instruction as an operandThe executio...

9.6k views

answered May 26, 2020

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NIELIT 2017 July Scientist B (CS) - Section B: 23
Comparing the time $T1$ taken for a single instruction on a pipelined CPU, with time $T2$ taken on a non-pipelined but identical CPU, we can say that ______ ? $T1=T2$ $T1>T2$ $T1<T2$ $T1$ is $T2$ plus time taken for one instruction fetch cycle

Comparing the time $T1$ taken for a single instruction on a pipelined CPU, with time $T2$ taken on a non-pipelined but identical CPU, we can say that ______ ?$T1=T2$$T1>T...

1.1k views

commented May 14, 2020

7 answers

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GATE CSE 2006 | Question: 68
Consider the relation enrolled (student, course) in which (student, course) is the primary key, and the relation paid (student, amount) where student is the primary key. Assume no null values and no foreign keys or integrity constraints. ... strictly fewer rows than Query$2$ There exist databases for which Query$4$ will encounter an integrity violation at runtime

Consider the relation enrolled (student, course) in which (student, course) is the primary key, and the relation paid (student, amount) where student is the primary key. ...

20.4k views

answered Apr 12, 2020

6 answers

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GATE CSE 2016 Set 1 | Question: 31
The size of the data count register of a $\text{DMA}$ controller is $16\;\text{bits}$. The processor needs to transfer a file of $29,154$ kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times ... needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is _________.

The size of the data count register of a $\text{DMA}$ controller is $16\;\text{bits}$. The processor needs to transfer a file of $29,154$ kilobytes from disk to main memo...

18.7k views

commented Mar 31, 2020

4 answers

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ISRO2011-16
Consider a direct mapped cache with $64$ blocks and a block size of $16$ bytes. To what block number does the byte address $1206$ map to does not map $6$ $11$ $54$

Consider a direct mapped cache with $64$ blocks and a block size of $16$ bytes. To what block number does the byte address $1206$ map todoes not map$6$$11$$54$

9.1k views

commented Mar 27, 2020

12 answers

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GATE CSE 2016 Set 2 | Question: 30
Suppose the functions $F$ and $G$ can be computed in $5$ and $3$ nanoseconds by functional units $U_{F}$ and $U_{G}$, respectively. Given two instances of $U_{F}$ and two instances of $U_{G}$, it is required to implement ... $1 \leq i \leq 10$. Ignoring all other delays, the minimum time required to complete this computation is ____________ nanoseconds.

Suppose the functions $F$ and $G$ can be computed in $5$ and $3$ nanoseconds by functional units $U_{F}$ and $U_{G}$, respectively. Given two instances of $U_{F}$ and two...

22.7k views

answered Mar 24, 2020

8 answers

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GATE CSE 2016 Set 1 | Question: 32
The stage delays in a $4$-stage pipeline are $800, 500, 400$ and $300$ picoseconds. The first stage (with delay $800$ picoseconds) is replaced with a functionality equivalent design involving two stages with respective delays $600$ and $350$ picoseconds. The throughput increase of the pipeline is ___________ percent.

The stage delays in a $4$-stage pipeline are $800, 500, 400$ and $300$ picoseconds. The first stage (with delay $800$ picoseconds) is replaced with a functionality equiva...

25.7k views

answered Mar 24, 2020

8 answers

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GATE CSE 2017 Set 2 | Question: 53
Consider a machine with a byte addressable main memory of $2^{32}$ bytes divided into blocks of size $32$ bytes. Assume that a direct mapped cache having $512$ cache lines is used with this machine. The size of the tag field in bits is _______

Consider a machine with a byte addressable main memory of $2^{32}$ bytes divided into blocks of size $32$ bytes. Assume that a direct mapped cache having $512$ cache line...

9.5k views

answered Mar 24, 2020

9 answers

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GATE CSE 2017 Set 1 | Question: 25
Consider a two-level cache hierarchy with $L1$ and $L2$ caches. An application incurs $1.4$ memory accesses per instruction on average. For this application, the miss rate of $L1$ cache is $0.1$; the $L2$ cache experiences, on average, $7$ misses per $1000$ instructions. The miss rate of $L2$ expressed correct to two decimal places is ________.

Consider a two-level cache hierarchy with $L1$ and $L2$ caches. An application incurs $1.4$ memory accesses per instruction on average. For this application, the miss rat...

24.4k views

answered Mar 24, 2020

7 answers

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GATE CSE 2018 | Question: 51
A processor has $16$ integer registers $\text{(R0, R1}, \ldots ,\text{ R15)}$ and $64$ floating point registers $\text{(F0, F1}, \ldots , \text{F63)}.$ It uses a $2\text{- byte}$ instruction format. There are four categories of ... $\text{(1F)}.$ The maximum value of $\text{N}$ is _________.

A processor has $16$ integer registers $\text{(R0, R1}, \ldots ,\text{ R15)}$ and $64$ floating point registers $\text{(F0, F1}, \ldots , \text{F63)}.$ It uses a $2\text{...

24.3k views

answered Mar 24, 2020

3 answers

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gate 2018 cs
physical address space of the omputer system is 2^p bytes , word size is 2^w bytes , cache memory has 2^n bytes and cache block size is 2^m words,k-way set associative is used for mapping from main memory to cache memory .the size of the tag bit is???

physical address space of the omputer system is 2^p bytes , word size is 2^w bytes , cache memory has 2^n bytes and cache block size is 2^m words,k-way set associative is...

3.5k views

answered Mar 24, 2020

7 answers

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GATE CSE 2018 | Question: 5
Consider the following processor design characteristics: Register-to-register arithmetic operations only Fixed-length instruction format Hardwired control unit Which of the characteristics above are used in the design of a RISC processor? I and II only II and III only I and III only I, II and III

Consider the following processor design characteristics:Register-to-register arithmetic operations onlyFixed-length instruction formatHardwired control unitWhich of the c...

12.1k views

answered Mar 24, 2020

4 answers

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GATE CSE 2018 | Question: 9
The following are some events that occur after a device controller issues an interrupt while process $L$ is under execution. P. The processor pushes the process status of $L$ onto the control stack Q. The processor finishes the execution of the ... based on the interrupt Which of the following is the correct order in which the events above occur? QPTRS PTRSQ TRPQS QTPRS

The following are some events that occur after a device controller issues an interrupt while process $L$ is under execution.P. The processor pushes the process status of ...

10.6k views

answered Mar 24, 2020

3 answers

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GATE CSE 2018 | Question: 23
A $32\text{-bit}$ wide main memory unit with a capacity of $1\;\textsf{GB}$ is built using $256\textsf{M} \times 4\text{-bit}$ DRAM chips. The number of rows of memory cells in the DRAM chip is $2^{14}$. The ... The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is _________.

A $32\text{-bit}$ wide main memory unit with a capacity of $1\;\textsf{GB}$ is built using $256\textsf{M} \times 4\text{-bit}$ DRAM chips. The number of rows of memory ce...

25.8k views

answered Mar 24, 2020

11 answers

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GATE CSE 2019 | Question: 45
A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept ... for the memory system when the program running on the processor issues a series of read operations is ______$\times 10^6$ bytes/sec.

A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a ...

20.5k views

answered Mar 24, 2020

2 answers

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UGC NET CSE | June 2019 | Part 2 | Question: 14
The fault can be easily diagnosed in the micro-program control unit using diagnostic tools by maintaining the contents of flags and counters registers and counters flags and registers flags, registers and counters

The fault can be easily diagnosed in the micro-program control unit using diagnostic tools by maintaining the contents offlags and countersregisters and countersflags and...

2.5k views

answered Mar 24, 2020

4 answers

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GATE CSE 2009 | Question: 8, UGCNET-June2012-III: 58
A CPU generally handles an interrupt by executing an interrupt service routine: As soon as an interrupt is raised. By checking the interrupt register at the end of fetch cycle. By checking the interrupt register after finishing the execution of the current instruction. By checking the interrupt register at fixed time intervals.

A CPU generally handles an interrupt by executing an interrupt service routine:As soon as an interrupt is raised.By checking the interrupt register at the end of fetch cy...

15.9k views

answered Mar 24, 2020

4 answers

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UGC NET CSE | June 2016 | Part 3 | Question: 5
The ____ addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are specified in the instruction. Base indexed Base indexed plus displacement Indexed Displacement

The ____ addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are spec...

3.1k views

answered Mar 24, 2020

2 answers

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UGC NET CSE | June 2016 | Part 3 | Question: 4
The Register that stores all interrupt requests is Interrupt mask register Interrupt service register Interrupt request register Status register

The Register that stores all interrupt requests isInterrupt mask registerInterrupt service registerInterrupt request registerStatus register

3.3k views

answered Mar 24, 2020

1 answer

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cache
In a particular system it is observed that, the cache performance get improved as a result of increasing the block size of the cache. The primary reason behing this is: 1. Program exhibits temporal locality 2. Programs have small working set 3. Read ... rather than write operation 4. Program exhibits spatial locality What would the answer to this Question ? asked in NIELIT assistant paper..

In a particular system it is observed that, the cache performance get improved as a result of increasing the block size of the cache. The primary reason behing this is:1....

1.2k views

answered Mar 23, 2020

3 answers

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RAM Chip
A RAM chip has 7 address line , 8 data lines and 2 chips select lines. Then the number of memory locations is ... a. 2^12 b.2^10 c.2^19 d.2^13 Plz describe with a proper diagram and significance of each lines.

A RAM chip has 7 address line , 8 data lines and 2 chips select lines. Then the number of memory locations is ...a. 2^12b.2^10c.2^19d.2^13Plz describe with a proper diagr...

5.9k views

answered Mar 23, 2020

4 answers

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NIELIT 2017 DEC Scientist B - Section B: 47
INCA(Increase register A by $1$) is an example of which of the following addressing mode? Immediate addressing Indirect addressing Implied addressing Relative addressing

INCA(Increase register A by $1$) is an example of which of the following addressing mode?Immediate addressingIndirect addressingImplied addressingRelative addressing

2.6k views

answered Mar 23, 2020

5 answers

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NIELIT 2017 DEC Scientist B - Section B: 13
Consider a non-pipelined machine with $6$ stages; the lengths of each stage are $\text{20ns, 10ns, 30ns,25ns, 40 ns}$ and $\text{15ns}$ respectively. Suppose for implementing the pipelining the machine adds $\text{5 ns}$ of overhead to each stage ... What is the speed up factor of the pipelining system (ignoring any hazard impact)? $7$ $14$ $3.11$ $6.22$

Consider a non-pipelined machine with $6$ stages; the lengths of each stage are $\text{20ns, 10ns, 30ns,25ns, 40 ns}$ and $\text{15ns}$ respectively. Suppose for implemen...

5.1k views

answered Mar 23, 2020

5 answers

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ISRO2015-77
In $\text{X = (M + N }\times \text{O)/(P} \times \text{Q})$, how many one-address instructions are required to evaluate it? $4$ $6$ $8$ $10$

In $\text{X = (M + N }\times \text{O)/(P} \times \text{Q})$, how many one-address instructions are required to evaluate it?$4$$6$$8$$10$

7.1k views

answered Mar 23, 2020

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