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Recent activity by vamp_vaibhav
1
answer
1
Number system digital
The r ’s complement of an n-digit decimal number N in base r is defined for all values of N except for N = 0. If the given number is (247)9, then its 9’s complement will be equal to ( _____ )9.
The r ’s complement of an n-digit decimal number N in base r is defined for all values of N except for N = 0. If the given number is (247)9, then its 9’s complement w...
1.7k
views
commented
Jan 6, 2018
Digital Logic
digital-logic
number
system
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–
3
answers
2
Programming
Consider the following program segment int main() { char *str = "GATECS"; printf("%d", madeeasy(str)); return 0; } int madeeasy(int *p1) { int *p2 = p1; while(*++p1); return p1-p2; } The out of above program will be ________. Assume that the object of data type int occupies 2 bytes.
Consider the following program segmentint main(){char *str = "GATECS";printf("%d", madeeasy(str));return 0;}int madeeasy(int *p1){int *p2 = p1;while(*++p1);return p1-p2;}...
1.1k
views
commented
Jan 5, 2018
Programming in C
programming
programming-in-c
made-easy-test-series
pointers
output
bad-question
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–
1
answer
3
MadeEasy Test Series 2018: Theory Of Computation - Finite Automata
Please help in this question i think B and C also true
Please help in this question i think B and C also true
811
views
commented
Jan 5, 2018
Theory of Computation
made-easy-test-series
theory-of-computation
finite-automata
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–
1
answer
4
MadeEasy Test Series 2017: Computer Networks - Congestion Control
Let the size of congestion window of a TCP connection be 38 KB when a timeout occurs. The propagation time of the connection is 100 msec and the maximum segment size used is 2 KB. The time taken (in msec) by the TCP connection to get back to 36 KB congestion window is ________.
Let the size of congestion window of a TCP connection be 38 KB when a timeout occurs. The propagation time of the connection is 100 msec and the maximum segment size used...
813
views
commented
Dec 30, 2017
Computer Networks
made-easy-test-series
computer-networks
congestion-control
madeeasy-testseries-2017
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–
1
answer
5
madeeasy
Given f(n) = θ(n), g(n) = Ω(n), h(n) = O(n). Then f(n) + [g(n) ⋅ h(n)] = ? A.O(n) B. θ(n) C. Ω(n) D. None of these Ans is given C Please explain how to solve such questions
Given f(n) = θ(n), g(n) = Ω(n), h(n) = O(n). Then f(n) + [g(n) ⋅ h(n)] = ?A.O(n)B. θ(n)C. Ω(n)D. None of theseAns is given CPlease explain how to solve such questio...
307
views
answered
Dec 30, 2017
Algorithms
algorithms
asymptotic-notation
made-easy-test-series
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–
2
answers
6
MadeEasy Test Series 2017: Computer Networks - Ip Packet
Consider station “A” send data to station “B”. Data frame contain MAC address, IP address and port address. Which of the following address may change on intermediate router A Destination IP address B Destination MAC C Source MAC D Source IP address
Consider station “A” send data to station “B”. Data frame contain MAC address, IP address and port address. Which of the following address may change on intermedi...
1.3k
views
commented
Dec 30, 2017
Computer Networks
computer-networks
made-easy-test-series
ip-packet
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–
0
answers
7
Min heap tree
Answer given : 1935360 but I m getting 3225600 please check..
Answer given : 1935360 but I m getting 3225600 please check..
588
views
commented
Dec 29, 2017
Programming in C
min
binary-heap
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–
0
answers
8
NIELIT SCIENTIST B 2017
The optimization phase in a compiler generally: (A) Reduced the space of the code (B) Optimizes the code to reduce execution time (C) Both (A) and (B) (D) Neither (A) nor (B)
The optimization phase in a compiler generally:(A) Reduced the space of the code(B) Optimizes the code to reduce execution time(C) Both (A) and (B)(D) Neither (A) nor (B)...
541
views
commented
Dec 29, 2017
1
answer
9
Digital Logic Doubt
The K-Map for a boolean function is shown below.The number of essential prime implicants for this function is ? 1 1 0 1 0 0 0 1 1 0 0 0 1 0 0 1 The answer given is 3. But I think it will be 4 - (0,8,10,2) , (0,1) , (3,6) and (8,12)
The K-Map for a boolean function is shown below.The number of essential prime implicants for this function is ?1101000110001001The answer given is 3. But I think it will ...
1.0k
views
commented
Dec 29, 2017
Digital Logic
digital-logic
k-map
boolean-algebra
digital-circuits
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–
0
answers
10
AceTestSeries: Programming & DS - Programming in C
300
views
commented
Dec 29, 2017
Programming in C
programming-in-c
programming
pointers
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–
0
answers
11
Sorting
Consider an execution of Quicksort with the first item of an array segment acting as pivot or splitter. After first pass of running quicksort on an array (Assume that we are sorting with increasing order)? 12,18,17,11,13,15,16,10 I want to know what will be the sequence for the first pass
Consider an execution of Quicksort with the first item of an array segment acting as pivot or splitter. After first pass of running quicksort on an array (Assume that we ...
571
views
commented
Dec 28, 2017
Algorithms
sorting
algorithms
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–
2
answers
12
B+ tree
The minimum number of elements (keys) that need to be inserted into a B+ tree with the order of internal node 3 [maximum child pointers per node] and leaf node 2 [maximum keys per node], to make it to reach 3-levels are __________.
The minimum number of elements (keys) that need to be inserted into a B+ tree with the order of internal node 3 [maximum child pointers per node] and leaf node 2 [maximum...
2.0k
views
commented
Dec 28, 2017
Databases
databases
bplustrees
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–
13
answers
13
Minimum number of tables to represent ER-Diagram
How many minimum relations required for given ER diagram ?
How many minimum relations required for given ER diagram ?
8.8k
views
commented
Dec 27, 2017
Databases
er-diagram
databases
er-to-relational
relational
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–
1
answer
14
Time to build a heap
If you are given a sorted list with n elements in ascending order. Then what will be the Time complexity to build a Min heap from the given array?
If you are given a sorted list with n elements in ascending order. Then what will be the Time complexity to build a Min heap from the given array?
1.5k
views
commented
Dec 27, 2017
DS
data-structures
binary-heap
time-complexity
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–
4
answers
15
Avg stall cycles per instruction
Suppose that in $500$ memory references there are $50$ misses in the first level cache and $20$ misses in second level cache. Assume miss penalty from the $L_{2}$ cache to memory is $100$ cycles. The hit time of $L_{2}$ cache is $20$ ... $L_{1}$ cache is $10$ cycles. If there are $2.5$ memory references per instruction. How many average stall cycle per instruction?
Suppose that in $500$ memory references there are $50$ misses in the first level cache and $20$ misses in second level cache. Assume miss penalty from the $L_{2}$ cache t...
4.7k
views
commented
Dec 27, 2017
CO and Architecture
co-and-architecture
stall
cache-memory
cycle
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–
0
answers
16
conflict serilizable
if i neglect T2 then its conflict sserilizable but if i dont neglect T2 then its not conflict serilizable ???
if i neglect T2 then its conflict sserilizable but if i dont neglect T2 then its not conflict serilizable ???
442
views
commented
Dec 27, 2017
1
answer
17
FOLLOW
Find Follow of F : $E\rightarrow E+T | T$ $T\rightarrow T*F | F$ $ F\rightarrow \left ( E \right ) |id$
Find Follow of F :$E\rightarrow E+T | T$$T\rightarrow T*F | F$$ F\rightarrow \left ( E \right ) |id$
354
views
commented
Dec 24, 2017
Compiler Design
compiler-design
parsing
first-and-follow
descriptive
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–
1
answer
18
RBR_Cn
which of the protocol is flow control but not error control? 1)stop n wait 2) go back n 3)selective repeate 4)simplest
which of the protocol is flow control but not error control?1)stop n wait2) go back n3)selective repeate4)simplest
396
views
answered
Dec 23, 2017
1
answer
19
test series
What is the view equivalent serial schedule for the following schedule R2(A); R1(A); W1(C); R3(C); W1(B); R4(B); W3(A); R4(C); W2(D); R2(B); W4(A); W4(B) T1 → T2 → T3 → T4. T2 → T1 → T3 → T4. T1 → T3 → T2 → T4. T4 → T2 → T3 → T1.
What is the view equivalent serial schedule for the following scheduleR2(A); R1(A); W1(C); R3(C); W1(B); R4(B); W3(A); R4(C); W2(D); R2(B); W4(A); W4(B) T1 → T2 → T3...
837
views
commented
Dec 23, 2017
1
answer
20
# made easy demo test #Q 23
my answer 5 plz check but answer given 4
my answer 5 plz check but answer given 4
328
views
commented
Dec 22, 2017
3
answers
21
user and kernel mdoe
can anyone tell what are different activities that are performed in kernel mode user mode how to change frm user mode to kernel mode and vice-versa,,
can anyone tell what are different activities that are performed in kernel modeuser modehow to change frm user mode to kernel mode and vice-versa,,
2.5k
views
commented
Dec 20, 2017
Operating System
operating-system
threads
process
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–
2
answers
22
Tokenization in lexical analysis
Consider the following C program: int main (void) { in/*this is an example*/z; double/*is it an error?*/y; print( “This is simple” ); return 0; } - How many Different tokens are there in the above code.
Consider the following C program: int main (void) { in/*this is an example*/z; double/*is it an error?*/y; print( “This is simple” ); return 0; }- How many Different ...
3.4k
views
commented
Dec 20, 2017
Compiler Design
compiler-design
compiler-tokenization
lexical-analysis
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–
1
answer
23
number of conflict serializable schedule
A) Number of conflict serializable schedules possible R4(a) R2(a) R3(a) W1(b) W2(a) R3(b) W2(b) B) NUmber of conflict serializABLE SCHEDULES possible by T1 and T2 T1 : R(a) W(a) R(b) W(b) T2 : R(a) W(a) R(b) W(b)
A) Number of conflict serializable schedules possibleR4(a) R2(a) R3(a) W1(b) W2(a) R3(b) W2(b)B) NUmber of conflict serializABLE SCHEDULES possible by T1 and T2T1 : R(...
2.0k
views
commented
Dec 20, 2017
1
answer
24
madeeasy
The following assembly code is to be executed in a 3-stage pipelined processor with hazard detection and resolution in each stage. The stage are IF, OF (one or more as required) and execution (including writeback operation). What are the number of possible RAW, WAW and WAR hazards in the execution of the code. A. 6,1,2 B. 5,1,2 C. 5,3,2 D. 5,3,3 Ans is B please explain with solution
The following assembly code is to be executed in a 3-stage pipelined processor with hazard detection and resolution in each stage. The stage are IF, OF (one or more as re...
1.5k
views
answered
Dec 19, 2017
1
answer
25
Normal Forms
1.1k
views
commented
Dec 18, 2017
Databases
databases
database-normalization
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–
4
answers
26
GATE CSE 2015 Set 2 | Question: 17
Consider a complete binary tree where the left and right subtrees of the root are max-heaps. The lower bound for the number of operations to convert the tree to a heap is $\Omega(\log n)$ $\Omega(n)$ $\Omega(n \log n)$ $\Omega(n^2)$
Consider a complete binary tree where the left and right subtrees of the root are max-heaps. The lower bound for the number of operations to convert the tree to a heap is...
16.2k
views
commented
Dec 18, 2017
DS
gatecse-2015-set2
data-structures
binary-heap
normal
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–
2
answers
27
Selective Repeat
Consider a network connecting two systems located 4000 kilometers apart. The bandwidth of the network is 64 Mbps. The propagation speed of the media is 2/3 of the speed of light in vacuum. It is needed to design selective repeat sliding window protocol ... processing delays at nodes are negligible. Then, the minimum size in bits of the sequence number field has to be _________.
Consider a network connecting two systems located 4000 kilometers apart. The bandwidth of the network is 64 Mbps. The propagation speed of the media is 2/3 of the speed o...
1.7k
views
commented
Dec 18, 2017
Computer Networks
computer-networks
selective-repeat
sliding-window
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–
3
answers
28
coa
Hit ratio of the cache memory read request is 85% and the cache memory is 5 times faster than main memory. Block size in memory organization is 4 words. The access time of the main memory is 72 ns per word. Write through protocol (simultaneous memory ... remaining for write operation. What is the average access time (in ns) of the memory when considering both read and write operations?
Hit ratio of the cache memory read request is 85% and the cache memory is 5 times faster than main memory. Block size in memory organization is 4 words. The access time o...
3.2k
views
commented
Dec 15, 2017
CO and Architecture
co-and-architecture
+
–
0
answers
29
Write through mechanism doubt
When the write through mechanism is implemented with simultaneous access, why write hit =1 and Tavg (write) = word updating time i.e max(Tc, Tm)?? I am getting confused.. Any help would be appreciated
When the write through mechanism is implemented with simultaneous access,why write hit =1 andTavg (write) = word updating time i.e max(Tc, Tm)?? I am getting confused.. ...
188
views
asked
Dec 15, 2017
1
answer
30
CO Test 1 q31
Consider a CPU that executes at a clock rate of 200MHz(5ns per cycle) with a single level cache. CPI execution i.e. CPI with ideal memory is 1.1. Instruction mix are 50% arithmetic/Logical, 30% load/store, 20% control instruction. Assume the cache miss rate is 15% and a miss penalty of 50 cycles. The number of times cpu with ideal memory is faster when no miss occurs _______
Consider a CPU that executes at a clock rate of 200MHz(5ns per cycle) with a single level cache. CPI execution i.e. CPI with ideal memory is 1.1. Instruction mix are 50% ...
2.6k
views
commented
Dec 15, 2017
CO and Architecture
co-and-architecture
cache-memory
+
–
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