Recent activity by viniit / GATE Overflow for GATE CSE

2 answers

1

GATE CSE 2022 | Question: 47
Consider a network with three routers $\text{P, Q, R}$ shown in the figure below. All the links have cost of unity. The routers exchange distance vector routing information and have converged on the routing tables, after which the link $\text{Q-R}$ ... off to one decimal place) between $\text{P}$ and $\text{Q},$ leading to count-to-infinity problem, is _______________.

Consider a network with three routers $\text{P, Q, R}$ shown in the figure below. All the links have cost of unity.The routers exchange distance vector routing informatio...

9.8k views

commented Jan 28, 2023

4 answers

2

GATE CSE 2022 | Question: 25
Consider the resolution of the domain name $\textsf{www.gate.org.in}$ by a $\text{DNS}$ resolver. Assume that no resource records are cached anywhere across the $\text{DNS}$ servers and that iterative query mechanism is used in the resolution. The number of $\text{DNS}$ query-response pairs involved in completely resolving the domain name is ________________.

Consider the resolution of the domain name $\textsf{www.gate.org.in}$ by a $\text{DNS}$ resolver. Assume that no resource records are cached anywhere across the $\text{DN...

11.3k views

commented Jan 28, 2023

3 answers

3

GATE CSE 2021 Set 2 | Question: 20
Consider a computer system with $\text{DMA}$ support. The $\text{DMA}$ module is transferring one $8$-bit character in one $\text{CPU}$ cycle from a device to memory through cycle stealing at regular intervals. Consider a $\text{2 MHz}$ ... $\text{DMA}$, the data transfer rate of the device is __________ bits per second.

Consider a computer system with $\text{DMA}$ support. The $\text{DMA}$ module is transferring one $8$-bit character in one $\text{CPU}$ cycle from a device to memory thro...

11.4k views

commented Jan 26, 2023

2 answers

4

GATE IT 2006 | Question: 78
A pipelined processor uses a $4-$stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The arithmetic operations as well as the load and store operations are carried out in the EX stage. The sequence of ... sequence of instructions are, respectively, $2, 2, 4$ $3, 2, 3$ $4, 2, 2$ $3, 3, 2$

A pipelined processor uses a $4-$stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). T...

15.4k views

commented Jan 24, 2023

1 answer

5

Recurrence Relation - Self Doubt
What is the recurrence relation for the ternary strings of length $n$ which can be constructed using 0,1 or 2 only such that the number of 0’s and number of 1's is odd ?

What is the recurrence relation for the ternary strings of length $n$ which can be constructed using 0,1 or 2 only such that the number of 0’s and number of 1's is od...

1.6k views

commented Dec 31, 2022

tags	tag:apple
author	user:martin
title	title:apple
content	content:apple
exclude	-tag:apple
force match	+apple
views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
is closed	isclosed:true