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Questions by vnc
0
votes
0
answers
1
TestBook TestSeries
(i)An ICMP message is generated if IP datagram header is corrupted (ii) No ICMP message is generated if IP address in data link frame is broadcast or multicast address. Both are correct Only (i) correct Only (ii) correct Both are incorrect
(i)An ICMP message is generated if IP datagram header is corrupted(ii) No ICMP message is generated if IP address in data link frame is broadcast or multicast address.Bot...
504
views
asked
Feb 4, 2017
Computer Networks
computer-networks
icmp
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–
3
votes
0
answers
2
TestBook TestSeries
in a binary search tree, the key with value 5 was searched after traversing nodes with values 1, 3, 4, 6, 7, 8, 9 not necessarily in this order. Lets P is the probability that 3rd element on the search path beginning from root is either 3 or 8, ... are the number of different orders possible in which given nodes can be traversed before finding node with value 5. Find N ∕ 10 + P
in a binary search tree, the key with value 5 was searched after traversing nodes with values 1, 3, 4, 6, 7, 8, 9 not necessarily in this order. Lets P is the probability...
469
views
asked
Jan 29, 2017
Programming in C
data-structures
binary-search-tree
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–
0
votes
1
answer
3
TestBook TestSeries
Consider the following statements : i) An ambiguous grammar can not generate DCFL. ii) An unambiguous grammar will always generate deterministic context free language. iii) Any non-empty language admits an ambiguous grammar. iv) All regular grammars are unambiguous. Which of the above is/are TRUE? i) and iv) only ii) and iii) only iii) only ii) and iv) only
Consider the following statements :i) An ambiguous grammar can not generate DCFL.ii) An unambiguous grammar will always generate deterministic context free language.iii) ...
394
views
asked
Jan 29, 2017
Theory of Computation
theory-of-computation
ambiguous
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–
0
votes
1
answer
4
TestBook TestSeries
TLB lookup time (th) = 20 ns TLB hit ratio (ht) = 99% Memory access time (ts) = 100 ns Page fault rate (hp) =0.05% Swap page time (in or out) (tp) = 5000,000 ns What is the effective access time (EAT) if we assume that all pages currently in main memory are dirty? 5118.91 ns 51.21 ns 5120.9 ns None of the above
TLB lookup time (th) = 20 nsTLB hit ratio (ht) = 99%Memory access time (ts) = 100 nsPage fault rate (hp) =0.05%Swap page time (in or out) (tp) = 5000,000 nsWhat is the ef...
733
views
asked
Jan 23, 2017
Operating System
operating-system
demand-paging
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–
2
votes
1
answer
5
TestBook Test Series
Let T be a B-tree of order m and height h. if n is the number of key elements in T then the maximum value of n is (m-1)h-1 (m-1)h-1+1 Mh-1 Mh+1+1
Let T be a B-tree of order m and height h. if n is the number of key elements in T then the maximum value of n is(m-1)h-1(m-1)h-1+1Mh-1Mh+1+1
1.4k
views
asked
Jan 13, 2017
Databases
databases
indexing
b-tree
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3
votes
3
answers
6
TestBook Test Series
If (65)x = (52)y, then what is the minimum value of x+y ?
If (65)x = (52)y, then what is the minimum value of x+y ?
977
views
asked
Jan 11, 2017
Digital Logic
digital-logic
number-representation
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–
1
votes
2
answers
7
TestBook Test Series
Consider the following information about a hypothetical organization. Assume the cache is physically addressed TLB:hit rate is 95%,access time is 1 cycle Cache: hit rate is 90%,access time is 1 cycle When TLB and cache both get miss,page fault rate is 1% ... cycles Page table is always kept in main memory. Compute the average memory access time? 1 cycle 2 cycle 3 cycle 4 cycle
Consider the following information about a hypothetical organization.Assume the cache is physically addressedTLB:hit rate is 95%,access time is 1 cycleCache: hit rate is ...
677
views
asked
Jan 11, 2017
CO and Architecture
co-and-architecture
cache-memory
page-fault
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–
1
votes
1
answer
8
TestBook Test Series
Assume a sequence of memory accesses is made that have a high degree of temporal locality, which one of these cache would be likely to have the best performance? A 4-way set associative cache with 2-byte blocks A 2-way set associative cache with 4-byte blocks A direct mapped cache with 4-byte blocks A direct mapped cache with 8-byte blocks
Assume a sequence of memory accesses is made that have a high degree of temporal locality, which one of these cache would be likely to have the best performance?A 4-way s...
308
views
asked
Jan 10, 2017
CO and Architecture
co-and-architecture
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2
votes
2
answers
9
MadeEasy Test Series
Consider the following schedule S : r1(A) w2(A) r3(A) w4(A) r5(A) w6(A) The number of schedules equal to given schedule(s) which not conflict equal to schedule(s) are _______.
Consider the following scheduleS : r1(A) w2(A) r3(A) w4(A) r5(A) w6(A)The number of schedules equal to given schedule(s) which not conflict equal to schedule(s) are _____...
1.2k
views
asked
Jan 10, 2017
Databases
databases
transaction-and-concurrency
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–
0
votes
1
answer
10
MadeEasy Subject Test: Databases - Transactions
Consider the following schedule : S::r1(A),r3(D),w1(B),r2(B),r4(B),w2(C),r5(C),w4(E),r5(E),w5(B) The number of serial schedules which are view equal to schedule (S) ___________.
Consider the following schedule :S::r1(A),r3(D),w1(B),r2(B),r4(B),w2(C),r5(C),w4(E),r5(E),w5(B)The number of serial schedules which are view equal to schedule (S) _______...
392
views
asked
Jan 10, 2017
Databases
databases
made-easy-test-series
transaction-and-concurrency
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0
votes
1
answer
11
Testbook Test series
How much memory is needed to store addition table of two 8 bit numbers 64Kx9 64Kx8 64Kx16 64Kx18
How much memory is needed to store addition table of two 8 bit numbers64Kx964Kx864Kx1664Kx18
383
views
asked
Jan 10, 2017
CO and Architecture
co-and-architecture
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