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2
answers
1
GATE CSE 1991 | Question: 03-ii
Advantage of synchronous sequential circuits over asynchronous ones is: faster operation ease of avoiding problems due to hazards lower hardware requirement better noise immunity none of the above
Advantage of synchronous sequential circuits over asynchronous ones is:faster operationease of avoiding problems due to hazardslower hardware requirementbetter noise immu...
8.6k
views
commented
May 8, 2017
Digital Logic
gate1991
digital-logic
normal
sequential-circuit
synchronous-asynchronous-circuits
multiple-selects
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1
answer
2
Ace workbook
627
views
commented
Sep 15, 2016
4
answers
3
division in relational algebra confirm plz
Suppose that cardinalities of relations $A$ and $B$ are $m$ and $n$ respectively, then the maximum cardinality of the resultant relation $A \div B$ is ($A$ divides $B$) (A) $m$ (B) $m-n$ (C) $\left \lceil {\frac{m}{n}} \right \rceil$ (D) $\left \lfloor {\frac{m}{n}} \right \rfloor$
Suppose that cardinalities of relations $A$ and $B$ are $m$ and $n$ respectively, then the maximum cardinality of the resultant relation $A \div B$ is ($A$ divides $B$)(A...
2.2k
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asked
Dec 16, 2015
Databases
databases
relational-algebra
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2
answers
4
TCP slow start right ans????????????
351
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asked
Dec 16, 2015
2
answers
5
dijkstra's negative weight yr ans required
643
views
commented
Dec 12, 2015
Algorithms
dijkstras-algorithm
test-series
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0
answers
6
O(klogk) time algorithm to find kth smallest element from a binary heap...
time complexit..? Q1. to find kth smallest element from a binary heap... a) O(k log k) b) O(k log n) c) O(1) d)O(nk) e) a,b both Q2. Print the biggest K elements in a given heap in O(K*log(K))____________? Q.3 how to determine if the kth largest element of the heap is greater than x____?
time complexit..?Q1. to find kth smallest element from a binary heap...a) O(k log k) b) O(k log n) c) O(1) d)O(nk) e) a,b bothQ2. Print the biggest K e...
1.5k
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commented
Dec 11, 2015
0
answers
7
successful and unsuccessful in hashing
i'm confused where and when to use these two formula, someone explain plz
i'm confused where and when to use these two formula, someone explain plz
352
views
asked
Dec 10, 2015
2
answers
8
Suppose host A want to send a large file to host B. ..
Suppose host A want to send a large file to host B. the path from host A to host B has 3 links of rates R1=512 Kbps, R2=2 Mbps and R3=1 Mbps. what is the throughput for the file transfer(in Kbytes per minuts)_____
Suppose host A want to send a large file to host B. the path from host A to host B has 3 links of rates R1=512 Kbps, R2=2 Mbps and R3=1 Mbps. what is the throughput for t...
2.0k
views
commented
Dec 10, 2015
2
answers
9
assume 10 Mbps Ethernet and two station A and B on it's same segment.......
assume 10 Mbps Ethernet and two station A and B on it's same segment. The RTT between two nodes is 650 bit times. A and B start transmitting frame and collision occure and both sends 30 bit jam signal. find the time at which both nodes A and B sense an idle channel(in micro sec)_____
assume 10 Mbps Ethernet and two station A and B on it's same segment. The RTT between two nodes is 650 bit times. A and B start transmitting frame and collision occure an...
1.1k
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asked
Dec 10, 2015
1
answer
10
dual mode operation- operating system
What is the purpose of dual-mode operation? To enable the operating system to take control of the processor. To save power. To protect the OS and hardware from corruption. To distinguish an ordinary user from a super user. what about 3rd option???option a is correct??
What is the purpose of dual-mode operation?To enable the operating system to take control of the processor.To save power.To protect the OS and hardware from corruption.To...
4.8k
views
asked
Dec 4, 2015
Operating System
operating-system
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1
answer
11
reducing misses in cache..
which of the following statement (if any) are generally true? 1. There is no way to reduce compulsory misses. 2. Full associative cache have no conflict misses. 3. In reducing misses, associativity is more important than capacity.
which of the following statement (if any) are generally true?1. There is no way to reduce compulsory misses.2. Full associative cache have no conflict misses.3. In reduci...
2.2k
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asked
Dec 4, 2015
6
answers
12
In how many ways can the entrepreneur assign 5 different tasks to 3 employees if each should get atleast 1 task ?
For this I considered cases1. 1 job each to 2 people and then jobs to a single person2. 2 jobs each to 2 people and then 1 job to a single person For the first case I di...
5.9k
views
commented
Dec 4, 2015
Combinatory
combinatory
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1
answer
13
find which of the following CFL which are not, plz discuss one by one..
1. L={ai bj ck | k=max{i,j}} 2. L={0n 1m | m≤n2} 3. L={0n 1m | m≠n2} 4. {0n 1m |m≠n, m≠2n, m≠3n} 5. {ai bj ck| i≠j or j≠k or i≠k} 6. {0,1}*-{(0n 1)n | n&ge ... regular then Lc={xz | (∃y)[|x|=|y|=|z|, xyz∈L]} is?? 9. L={0,1}*-{(0m 1m)n | m,n≥1}
1. L={ai bj ck | k=max{i,j}}2. L={0n 1m | m≤n2}3. L={0n 1m | m≠n2}4. {0n 1m |m≠n, m≠2n, m≠3n}5. {ai bj ck| i≠j or j≠k or i≠k}6. {0,1}*-{(0n 1)n | ...
481
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asked
Dec 3, 2015
1
answer
14
cache miss in two way set associative ..
in this question as said block size contains two 32 bit word, and byte addressable, so each time fetching a block from main mem will fetch 8 byte, so my doubt is, BCD address 200 and 204 in decimal 512 and 516, fetching block at ... 200 also contains bytes at address 204 so for 200 miss and 204 will next time, bcz 204 already fetched during fetching of 200
in this question as said block size contains two 32 bit word, and byte addressable, so each time fetching a block from main mem will fetch 8 byte, so my doubt is, BCD add...
749
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edited
Dec 2, 2015
1
answer
15
database indexing, "what is binary search on data"...not getting what he want to ask
674
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asked
Dec 2, 2015
3
answers
16
Viable Prefix
2.7k
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commented
Dec 2, 2015
Compiler Design
compiler-design
parsing
viable-prefix
test-series
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1
answer
17
LRU plz explain
406
views
asked
Dec 2, 2015
1
answer
18
maximum no of vertices explain plz
Q1. Assume that G is a simple graph of 20 edges, 6 vertices of degree 4 and other nodes have degrees more than 5, then the maximum no of vertices of G is______ Q2. all thread must wait whenever any critical section is occupied----how this is false?
Q1. Assume that G is a simple graph of 20 edges, 6 vertices of degree 4 and other nodes have degrees more than 5, then the maximum no of vertices of G is______Q2. all th...
413
views
answer selected
Dec 1, 2015
1
answer
19
DMA Q2
The MegaGiga hard disk rotates at $10000$ rpm ($6$ ms/rot) with a seek time given by = $1+0.001$tmsec, where $t$ is the number of tracks the arm seeks. Assume a block size of $512$ bytes, $1024$ sector/track, $8192$ tracks, and $4$ platters. The disk has a $16$ MB ... $100 \textsf{ MB/sec}$. Estimate the worst case delay to read $512$ bytes from this disk. $25$ms $15.2$ms $14.9$ms $26.3$ms
The MegaGiga hard disk rotates at $10000$ rpm ($6$ ms/rot) with a seek time given by = $1+0.001$tmsec, where $t$ is the number of tracks the arm seeks. Assume a block siz...
732
views
answer selected
Dec 1, 2015
CO and Architecture
dma
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1
answer
20
associative cache
Consider a 32 bit processor that has an on chip 16Kbyte 4 way set associative cache. assume that cache has a size of four 32 bit words. the set no in the cache to which the word from memory location FFFAE8FA is mapped_________
Consider a 32 bit processor that has an on chip 16Kbyte 4 way set associative cache. assume that cache has a size of four 32 bit words. the set no in the cache to which ...
768
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answer selected
Nov 30, 2015
2
answers
21
DMA
consider the system in which cycle time is 500 ns. transfer of bus control in either direction, from processor to I/O device or vice versa, takes 250 ns.one of the I/O device has a data transfer rate of 50 kB/s and employees DMA. data are transferred one byte at a time. The time(in ms) would the device tie-up the bus when transferring block of 128 bytes is _______
consider the system in which cycle time is 500 ns. transfer of bus control in either direction, from processor to I/O device or vice versa, takes 250 ns.one of the I/O de...
649
views
commented
Nov 30, 2015
1
answer
22
max no of saddle point.. explain
A $n \times n$ matrix is given and an element $a_{ij}$ is called saddle point if all the element in the $i^{th}$ row are less than $a_{ij}$ and all the element in $j^{th}$ column are greater than $a_{ij}$. How many maximum no of saddle point are possible. $2$ $3$ $n$ $1$
A $n \times n$ matrix is given and an element $a_{ij}$ is called saddle point if all the element in the $i^{th}$ row are less than $a_{ij}$ and all the element in $j^{th}...
463
views
asked
Nov 30, 2015
Calculus
engineering-mathematics
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1
answer
23
"TLB with physically addressed cache" plz write expression for avg mem access time???
Given the following information: TLB hit rate $95$%, TLB access time is $1$ cycle. Cache hit rate $90$%, cache access time is $1$ cycle. When TLB and cache both get miss; page fault rate ... average memory access latencies when the cache is physically addressed (in cycles) (up to $2$ decimal places) is__________.
Given the following information:TLB hit rate $95$%, TLB access time is $1$ cycle.Cache hit rate $90$%, cache access time is $1$ cycle.When TLB and cache both get miss; pa...
509
views
asked
Nov 28, 2015
CO and Architecture
co-and-architecture
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–
1
answer
24
effect on increasing no stages in pipeline....
In a CPU, what is the benefit of having many pipeline stages? Why speedup reduces with increase in number of pipeline stages? Why increased pipeline depth does not always mean increased throughput? why long pipeline lead to lower CPI? what will be the effect on friquency when of of stages increased.
In a CPU, what is the benefit of having many pipeline stages?Why speedup reduces with increase in number of pipeline stages?Why increased pipeline depth does not always m...
2.8k
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asked
Nov 25, 2015
3
answers
25
no of clock cycle required for bellow figure "in case of no operand forwarding used" ??
1.3k
views
commented
Nov 25, 2015
2
answers
26
TCP, find avg no of packet in queue..?
Consider a $10^{7}$ bps link that is $400$km long, with a queue large enough to hold $2000$ packets. Assume that packets arrive at the queue with an average rate of $4000$ packets per second and that the average packet length is $2000$ bits. Find the average number of packets in the queue?
Consider a $10^{7}$ bps link that is $400$km long, with a queue large enough to hold $2000$ packets. Assume that packets arrive at the queue with an average rate of $4000...
642
views
asked
Nov 25, 2015
1
answer
27
madeeasy test TCP total overhead
What is the total over header bits (Headers & Retransmission) with data frames consisting of $40$ bit header and $3960$ data bits. ACK frames never occur. NAK frames are $40$ bits, the error rate for frame is $2$% and for NAK frame is negligible. $80.4$ $80.8$ $160.4$ None of these.
What is the total over header bits (Headers & Retransmission) with data frames consisting of $40$ bit header and $3960$ data bits. ACK frames never occur. NAK frames are ...
420
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asked
Nov 24, 2015
1
answer
28
madeeasy test2015
378
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commented
Nov 23, 2015
1
answer
29
TEST SERIES question
Given Ts : Transfer time. b: Number of bytes to be transfered. N: Number of bytes on a track. r: Rotational speed. Which of the following expression gives the total avg access time? a. Ts+(r/2)+(rb/N) b. Ts+(1/2r)+(rb/N) c. Ts+(1/2r)+(N/rb) d. Ts+(1/2r)+(b/rN)
Given Ts : Transfer time.b: Number of bytes to be transfered.N: Number of bytes on a track.r: Rotational speed.Which of the following expression gives the total avg acces...
333
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answer selected
Nov 22, 2015
2
answers
30
madeeasy test
A byte addressable system with 16-bit address lines with a 2-way set associative, write back cache with perfect LRU replacement. Assume 1 valid bit and 1 dirt bit maintains for each block. The tag store requires a total of 4352 bits of storage. what is the block size of the cache?[in bytes]. ans________
A byte addressable system with 16-bit address lines with a 2-way set associative, write back cache with perfect LRU replacement. Assume 1 valid bit and 1 dirt bit maintai...
1.5k
views
comment edited
Nov 20, 2015
CO and Architecture
co-and-architecture
cache-memory
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