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Consider a $33$ MHz cpu based system. What is the number of wait states required if it is interfaced with a $60$ ns memory? Assume a maximum of $10$ ns delay for additional circuitry like buffering and decoding.

  1. $0$          
  2. $1$            
  3. $2$            
  4. $3$
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A wait state is a situation in which a computer program or processor is waiting for the completion of some event before resuming activity. A program or process in a wait state is inactive for the duration of the wait stat
When a computer processor works at a faster clock speed (expressed in MHz or millions of cycles per second) than the random access memory ( RAM ) that sends it instructions, it is set to go into a wait state for one or more clock cycles so that it is synchronized with RAM speed. In general, the more time a processor spends in wait states, the slower the performance of that processor.
From the given question, we will get total memory access time by combining access time and delay.
CPU frequency = 33 MHz
1 clock time = 1 / (33 MHz) = (1/33)*10-6 = 30.30 ns.
Total memory access time = 60 ns + 10 ns = 70 ns.
Total number of wait states = Total number of cycle needed
= Total memory access time / CPU frequency
=70 ns / (30.30 ns) = 2.31 (equivalent to 3 cycles)
Answer:

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