GATE CSE 1998 | Question: 1.20

Question

Which of the following is true?

• A. Unless enabled, a CPU will not be able to process interrupts.

• B. Loop instructions cannot be interrupted till they complete.

• C. A processor checks for interrupts before executing a new instruction.

• D. Only level triggered interrupts are possible on microprocessors.

Comments

Divy Kala

there also it should check.

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option c is ambiguous ,is it execution cyle or execution of whole instruction.

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@Sachin886 yes i think it must be specified 

Answer 1

Answer is (A).

Options (B) and (D) are obviously false.

A processor checks for the interrupt before FETCHING an instruction, so option (C) is also false.

Comments

This might seem funny but i took the ‘enabling’ in option A to be of the CPU itself and not the interrupts. Can the option A mean this?

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Fetching comes before execution → checks for interrupts “before execution” → checks for interrupts before “decoding” ..so on
So in a MSQ sence opt (C) is also right

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@KartikGawande obviously yess bro , because if the CPU is disabled then how will the interuppt even be processed.

Answer 2

• “Unless enabled, a CPU will not be able to process interrupts.”

  • Typically, CPUs have an Interrupt Enable (IE) bit or similar mechanism (e.g., IF flag in x86). Agar yeh disabled hai, toh CPU interrupts ko service nahi karega.
  • Verdict: True 

• “Loop instructions cannot be interrupted till they complete.”

  • Koi bhi instruction (chahe loop ho ya koi doosra) interrupt ho sakta hai; CPU pipeline can be broken if an interrupt is recognized and enabled. “Loop instruction” aisi koi special cheez nahi hai jo interrupt se bach jaye.
  • Verdict: False.

• “A processor checks for interrupts before executing a new instruction.”

  • Commonly, interrupts are checked at instruction boundaries (har nayi instruction fetch/execute se pehle). Agar koi interrupt pending hai aur enable bhi hai, toh CPU control interrupt handler pe jaata hai.
  • Verdict: Trueon most typical CPU designs.

• “Only level triggered interrupts are possible on microprocessors.”

  • Yeh galat hai, kyunki bahut se processors edge‐triggered interrupts bhi support karte hain (for example, Intel 8086 me INTR is level‐triggered, lekin NMI ya kuch external interrupts kabhi edge‐triggered bhi ho sakte hain; modern controllers can support both).
  • Verdict: False.

CPU har instruction ki completion par check karta hai ki koi interrupt pending to nahin. Agar interrupt enable hai aur pending hai, toh next instruction normal flow se fetch/execute karne ke bajay, CPU interrupt service routine (ISR) ki taraf branch kar deta hai.

• Issi ko kai jagah bola jaata hai “processor checks for interrupts at instruction boundaries”.
• A practical way of saying the same thing is “before fetching the next instruction,”

• Agar aap pipeline stages ko dekho (Fetch → Decode → Execute → Memory → Writeback, etc.), toh “checking interrupts before fetching the next instruction” often means the CPU ensures the previous instruction has completed, and then it decides: “Am I going to fetch from the normal PC, or jump to the interrupt vector?”
• In a pipelined CPU, the exact stage jahan interrupt detect hota hai hardware design pe depend karta hai, par conceptually hum kehte hain:

  CPU completes the current instruction, checks interrupts, then either continues normal fetch or fetches the ISR start address.

• “A processor checks for the interrupt before fetching an instruction” generally aligns with the typical textbook explanation:“Interrupts are recognized at instruction boundaries, so the next fetch may go to the interrupt routine.”

Comments

whenever you see English +HinEnglish it's definelty going to be @Kshitij Sharma  with easy explanation.

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option c is false
Why Option C is Wrong: The statement "A processor checks for interrupts before executing a new instruction" is incorrect. It implies that the processor might Fetch and Decode an instruction, and then check for an interrupt before the Execute phase.
But In actual scenario , it checks only after executing the current instruction and before fetching the next instruction. 

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ayush18288

I too thought from the wording of the option that "It checks the interrupt once all the machine cycles of the instruction is done"
Thank god I stumbled upon this question...

The presence of interrupt is indeed verified once all the machine cycle of the current instruction is done..But,
If our Instruction has  IF  ID  EX  MA  WB , then the interrupt is checked only after Write Back and before the Instruction fetch of new Instruction

Answer 3

are both option (a) and (c)  TRUE .... explain ???
Option (c) “Polling is like picking up your phone every few seconds to see if you have a call. Interrupts are like waiting for the phone to ring.”

CPU senses (checks) interrupt request line after every instruction; if raised,.... correct me

http://www.cs.toronto.edu/~demke/469F.06/Lectures/Lecture6.pdf or archive

Comments

@Swami Patil

Option C is wrong because we know that instruction has to pass through various phases(fetching, decoding, executing, writeback ), after completion of instruction CPU has to check for interrupts.

CPU can not check interrupts after executing phase..

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Why are we assuming it to be a pipelined system?

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Anybody with this toronto pdf? It's saying forbidden