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Search results for addressing-modes
0
votes
1
answer
21
Addressing mode
lea
384
views
lea
asked
Jun 12, 2023
Operating System
operating-system
addressing-modes
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–
40
votes
4
answers
22
GATE CSE 1998 | Question: 1.19
Which of the following addressing modes permits relocation without any change whatsoever in the code? Indirect addressing Indexed addressing Base register addressing PC relative addressing
Which of the following addressing modes permits relocation without any change whatsoever in the code?Indirect addressingIndexed addressingBase register addressingPC relat...
Kathleen
11.1k
views
Kathleen
asked
Sep 25, 2014
CO and Architecture
gate1998
co-and-architecture
addressing-modes
easy
+
–
49
votes
3
answers
23
GATE CSE 2017 Set 1 | Question: 11
Consider the $C$ struct defined below: struct data { int marks [100]; char grade; int cnumber; }; struct data student; The base address of student is available in register $R1$. The field student.grade can be accessed efficiently using: Post-increment ... mode, $X(R1)$, where $X$ is an offset represented in $2's$ complement $16\text{-bit}$ representation
Consider the $C$ struct defined below:struct data { int marks [100]; char grade; int cnumber; }; struct data student;The base address of student is available in register...
Arjun
14.6k
views
Arjun
asked
Feb 14, 2017
CO and Architecture
gatecse-2017-set1
co-and-architecture
addressing-modes
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–
6
votes
4
answers
24
ISRO2020-1
The immediate addressing mode can be used for Loading internal registers with initial values Perform arithmetic or logical operation on data contained in instructions Which of the following is true? Only $1$ Only $2$ Both $1$ and $2$ Immediate mode refers to data in cache
The immediate addressing mode can be used forLoading internal registers with initial valuesPerform arithmetic or logical operation on data contained in instructionsWhich ...
Satbir
4.1k
views
Satbir
asked
Jan 13, 2020
CO and Architecture
isro-2020
co-and-architecture
normal
addressing-modes
+
–
31
votes
3
answers
25
GATE CSE 1993 | Question: 10
The instruction format of a CPU is: $\text{Mode}$ and $\text{RegR}$ together specify the operand. $\text{RegR}$ specifies a CPU register and $\text{Mode}$ specifies an addressing mode. In particular, $\text{Mode}=2$ specifies that ... address of the operand? Assuming that is a non-jump instruction, what are the contents of PC after the execution of this instruction?
The instruction format of a CPU is:$\text{Mode}$ and $\text{RegR}$ together specify the operand. $\text{RegR}$ specifies a CPU register and $\text{Mode}$ specifies an add...
Kathleen
7.2k
views
Kathleen
asked
Sep 29, 2014
CO and Architecture
gate1993
co-and-architecture
addressing-modes
normal
descriptive
+
–
56
votes
3
answers
26
GATE IT 2006 | Question: 39, ISRO2009-42
Which of the following statements about relative addressing mode is FALSE? It enables reduced instruction size It allows indexing of array element with same instruction It enables easy relocation of data It enables faster address calculation than absolute addressing
Which of the following statements about relative addressing mode is FALSE?It enables reduced instruction sizeIt allows indexing of array element with same instructionIt e...
Ishrat Jahan
15.0k
views
Ishrat Jahan
asked
Oct 31, 2014
CO and Architecture
gateit-2006
co-and-architecture
addressing-modes
normal
isro2009
+
–
0
votes
0
answers
27
Relative Addressing Mode
Consider 3-word long jump instruction designed with PC-relative addressing mode, stored in the memory with a starting address of (2000)$_{10}$. Address field of an instruction contains (4000)$_{10}.$ Which of the following statements are true in the instruction ... where operand is stored, then how we can we assign it to PC? PC should be 2003 at the end of execution right?
Consider 3-word long jump instruction designed with PC-relative addressing mode, stored in the memory with a starting address of (2000)$_{10}$. Address field of an instru...
Chaitanya Kale
644
views
Chaitanya Kale
asked
Feb 13, 2023
CO and Architecture
addressing-modes
co-and-architecture
made-easy-test-series
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0
votes
1
answer
28
consider 16tb disk that uses 4kb block and free list method. how many block address can be stored in a block
Shubham Kathiriya
629
views
Shubham Kathiriya
asked
Jan 26, 2023
Operating System
operating-system
addressing-modes
+
–
0
votes
1
answer
29
Addressing Modes
When we write MOV #1000 , it means we are writing the value 1000 into the accumulator. But when we write MOV 1000 here 1000 refers to address of what ? register or MM ? (knowing that MOV works only between registers).
When we write MOV #1000 , it means we are writing the value 1000 into the accumulator. But when we write MOV 1000 here 1000 refers to address of what ? register or MM ? (...
Aaryan_Sharma
387
views
Aaryan_Sharma
asked
Dec 30, 2022
CO and Architecture
co-and-architecture
addressing-modes
goclasses
+
–
40
votes
3
answers
30
GATE IT 2006 | Question: 40
The memory locations $1000,1001$ and $1020$ have data values $18,1$ and $16$ ... value $20$ Memory location $1020$ has value $20$ Memory location $1021$ has value $20$ Memory location $1001$ has value $20$
The memory locations $1000,1001$ and $1020$ have data values $18,1$ and $16$ respectively before the following program is executed.$$\begin{array}{ll} \text{MOVI} & \text...
Ishrat Jahan
17.4k
views
Ishrat Jahan
asked
Oct 31, 2014
CO and Architecture
gateit-2006
co-and-architecture
addressing-modes
normal
+
–
1
votes
2
answers
31
NIELIT STA 2021
The addressing mode / s, which uses the PC instead of a general-purpose register is: Indexed with offset Relative Direct Both Indexed with offset and direct
The addressing mode / s, which uses the PC instead of a general-purpose register is: Indexed with offset RelativeDirectBoth Indexed with offset and direct
rsansiya111
1.6k
views
rsansiya111
asked
Dec 6, 2021
CO and Architecture
co-and-architecture
addressing-modes
+
–
0
votes
0
answers
32
Best Open Video Playlist for Addressing Modes Topic | CO & A
Please list out the best free available video playlist for Addressing Modes from CO & A as an answer here (only one playlist per answer). We'll then select the best playlist and add to GO classroom video lists. You ... but standard ones are more likely to be selected as best. For the full list of selected videos please see here
Please list out the best free available video playlist for Addressing Modes from CO & A as an answer here (only one playlist per answer). We'll then select the best playl...
makhdoom ghaya
269
views
makhdoom ghaya
asked
Aug 15, 2022
Study Resources
go-classroom
video-links
missing-videos
free-videos
addressing-modes
+
–
3
votes
2
answers
33
addressing modes
A certain machine uses expanding opcode. It has 16-bit instructions and 6-bit addresses. It supports one address and two address instructions only. If there are ‘n’ two address instructions, the maximum number of one address instruction is (a) 2^16 – n (b) 2^10 – n (c) (2^4 – n) × 2^6 (d) 2^10
A certain machine uses expanding opcode. It has 16-bit instructions and 6-bit addresses. It supports one address and two address instructions only. If there are ‘n’ t...
Sunil8860
2.1k
views
Sunil8860
asked
Aug 6, 2017
CO and Architecture
addressing-modes
co-and-architecture
+
–
2
votes
1
answer
34
Addressing modes
Could you please explain How we can implement indirect addressing mode using Index addressing mode.. and vice versa..??
Could you please explain How we can implement indirect addressing mode using Index addressing mode.. and vice versa..??
Subbu.
527
views
Subbu.
asked
Jul 14, 2022
CO and Architecture
co-and-architecture
addressing-modes
+
–
0
votes
1
answer
35
#addressing modes
How to implement indirect addressing mode using register indirect addressing mode???
How to implement indirect addressing mode using register indirect addressing mode???
Subbu.
352
views
Subbu.
asked
Aug 3, 2022
CO and Architecture
co-and-architecture
addressing-modes
+
–
3
votes
1
answer
36
Effective Address Calculation
Plz discuss every part with detailed solution with diagram .
Plz discuss every part with detailed solution with diagram .
dragonball
19.8k
views
dragonball
asked
Jan 2, 2018
CO and Architecture
co-and-architecture
addressing-modes
+
–
41
votes
4
answers
37
GATE CSE 2004 | Question: 20
Which of the following addressing modes are suitable for program relocation at run time? Absolute addressing Based addressing Relative addressing Indirect addressing I and IV I and II II and III I, II and IV
Which of the following addressing modes are suitable for program relocation at run time?Absolute addressingBased addressingRelative addressingIndirect addressingI and IVI...
Kathleen
12.3k
views
Kathleen
asked
Sep 18, 2014
CO and Architecture
gatecse-2004
co-and-architecture
addressing-modes
easy
+
–
4
votes
5
answers
38
ISRO2020-15
A stack organized computer is characterised by instructions with indirect addressing direct addressing zero addressing index addressing
A stack organized computer is characterised by instructions withindirect addressingdirect addressingzero addressingindex addressing
Satbir
4.4k
views
Satbir
asked
Jan 13, 2020
CO and Architecture
isro-2020
co-and-architecture
addressing-modes
normal
+
–
0
votes
1
answer
39
Applied Test Series
Consider a processor that includes a base with indexing addressing mode. Suppose an instruction is encountered that employs this addressing mode and specifies a displacement of 1970, in decimal. Currently the base and index register contain the decimal numbers 48,022 and 8, respectively. What is the address of the operand?
Consider a processor that includes a base with indexing addressing mode. Suppose an instruction is encountered that employs this addressing mode and specifies a displacem...
Sagar475
1.2k
views
Sagar475
asked
Jan 7, 2022
CO and Architecture
co-and-architecture
addressing-modes
+
–
0
votes
2
answers
40
TestBook- Addressing Modes
A register to register machine supports 2–address, 1-address and zero–address instructions. Instruction register size is 24 bits and register set size is 480. If there are 48 2–address instructions and 2048 zero – address instructions then what is the maximum possible number of 1 – address instruction?
A register to register machine supports 2–address, 1-address and zero–address instructions. Instruction register size is 24 bits and register set size is 480.If there...
anjali007
508
views
anjali007
asked
Dec 4, 2018
CO and Architecture
co-and-architecture
addressing-modes
testbook-test-series
numerical-answers
+
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