If both R =0 ,S=0 ,then both Q and Q’ tend to be ‘1’. NAND gate says if both inputs are 1,the output is 0. The logic of the circuit (Q’ is complement of Q) not satisfied, Logic state is said to be indeterminate state or racing state. Each state, Q =‘1’and Q =‘0’, and Q =‘0’, Q=‘1’ trying to race through so “RACE CONDITION” occurs and output become unstable. So ans is (D).