Question

I1 : Load R0,3(R1) I2:Sub R3,R0,R4 I3: Mul R5,R0,R6 I4: Div R7,R0,R8 .How many cycles are needed to complete above instruction using RISC pipeline, where all stages take 1 cycle

Answer 1

IF :instruction fetch 

ID :instruction decode

EX : execution

MA: memory access

WB: write back

 I1:Load R0,3(R1)

I2:Sub R3,R0,R4

I3: Mul R5,R0,R6

I4: Div R7,R0,R8 

	1	2	3	4	5	6	7	8	9	10 (cycle)
I1	IF	ID	EX	MA	WB
I2		IF	ID	-----------		EX	MA	WB
I3			IF			ID	EX	MA	Wb
I4						IF	ID	EX	MA	WB

so 10 cycles required..

Comments

see for the execution of the instruction I2 firstly data should be available in  ID  stage of I2 instructionID  is instruction decode which means i2 instruction check the opcode and all the dependent and independent variables which is going to be used in EX stage of the I2 instruction so to check that dependent variable from previous instruction iefrom  I1 it will wait for some time after when it is available than it will go in EXECUTION STAGE ...

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@Kunal Sir:Plz xplain the reason behind the stalls in ur frst answer diagram.

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For I3 why ID stage cant be done in 4th clock cycle

Answer 2

	1	2	3	4	5	6	7	8	9	10
I1	IF	ID	EX	MA	WB
I2		IF	ID	------	EX	MA	WB
I3			IF	ID	----	EX	MA	WB
I4				IF	ID	----	EX	MA	WB

 

 

THEREFORE total 9 cycles needed.
Since this is RISC pipeline by default it will use operand forwarding and we will witness operand forwarding between I1’s  MA and I2’s EX where dependent operand will be directly forwarded and thus other answer is completely wrong