0 votes 0 votes how to approach this question? i didn't understand the question Digital Logic test-series + – Prince Sindhiya asked Oct 6, 2018 • edited Oct 6, 2018 by Prince Sindhiya Prince Sindhiya 351 views answer comment Share Follow See all 4 Comments See all 4 4 Comments reply Shaik Masthan commented Oct 6, 2018 reply Follow Share i am getting 10. what is the answer? 0 votes 0 votes Prince Sindhiya commented Oct 7, 2018 reply Follow Share Answer is 11 0 votes 0 votes Shaik Masthan commented Oct 7, 2018 reply Follow Share sorry.... it should be 11 due to clear input value passed to the FF when clock pulse is applied only ==> wait for next clock pulse. 0 votes 0 votes akshat sharma commented Oct 7, 2018 reply Follow Share when MSB Qa=1 ,Qc=1 then clear =0 which will be the initial position 0000 after 11 cycle it wll repeat so on 0 votes 0 votes Please log in or register to add a comment.
Best answer 1 votes 1 votes CLR will set iff Qa and Qc = 1 Qa Qb Qc Qd CLR 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 0 0 0 0 0 Dharmendra Lodhi answered Oct 7, 2018 • selected Oct 7, 2018 by Prince Sindhiya Dharmendra Lodhi comment Share Follow See all 0 reply Please log in or register to add a comment.
